From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B79DC282D1 for ; Thu, 6 Mar 2025 11:10:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 79E6780F9E; Thu, 6 Mar 2025 12:10:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 27FD3810DC; Thu, 6 Mar 2025 12:10:07 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 94E1180F4C for ; Thu, 6 Mar 2025 12:10:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTPS id 526B9Abu086328 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Thu, 6 Mar 2025 19:09:10 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02 (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 6 Mar 2025 19:09:10 +0800 Date: Thu, 6 Mar 2025 19:09:06 +0800 From: Leo Liang To: Yao Zi CC: Rick Chen , Tom Rini , Bin Meng , Paul Walmsley , "Palmer Dabbelt" , Anup Patel , Atish Patra , Green Wan , Minda Chen , Simon Glass , "Angelo Dureghello" , Ilias Apalodimas , Heinrich Schuchardt , Subject: Re: [PATCH 5/5] riscv: select OF_HAS_PRIOR_STAGE by default if SBI is enabled Message-ID: References: <20250227144734.61458-1-ziyao@disroot.org> <20250227144734.61458-6-ziyao@disroot.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250227144734.61458-6-ziyao@disroot.org> User-Agent: Mutt/2.2.10 (e0e92c31) (2023-03-25) X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 526B9Abu086328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Thu, Feb 27, 2025 at 02:47:33PM +0000, Yao Zi wrote: > Availability of RISC-V SBI service implies a prior stage exists. As SBI > firmware usually passes a FDT to the loaded program, let's select > OF_HAS_PRIOR_STAGE if SBI is enabled. > > With previously added fallback version of board_fdt_blob_setup, S-Mode > RISC-V ports use the SBI-provided FDT by default. This covers the most > common usecase, where a SPL (probably the U-Boot one) selects proper > devicetree, loads SBI and U-Boot then invokes SBI with the devicetree. > > Signed-off-by: Yao Zi > Reviewed-by: Leo Yu-Chi Liang > --- > arch/riscv/Kconfig | 1 + > 1 file changed, 1 insertion(+) Hi Yao, This patch would fail some of the CI tests. I will take other patches from this patchset first, and could you take a look at the CI tests issue ? (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/1049827) Best regards, Leo