From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECC02C77B7F for ; Fri, 19 May 2023 12:56:49 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A457084785; Fri, 19 May 2023 14:56:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="EWIP3tLm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 899CD8617C; Fri, 19 May 2023 14:56:45 +0200 (CEST) Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 75743846BF for ; Fri, 19 May 2023 14:56:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ilias.apalodimas@linaro.org Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f42711865eso20565395e9.0 for ; Fri, 19 May 2023 05:56:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684501002; x=1687093002; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=0jD85a1byx0I7vZDl4DIHafULFBs2J0mGqz+tke9Mq8=; b=EWIP3tLmogzIFTF+slYh3jxwGJ8Ahy68zndUCpzArJA2Xp4K3uR0iiLI8DbB94787Z A/DI837t0xwEvPUgAhnwWEhNoxxfeBkCT2ewzwx8V7dkRrGGdn0BtcQuw9TyqTfIZVFa +LpaS5CdlGJcNUi3805Yo7kwu5tG7s9/HYltt35hkFqw/eykdyj4eE15P/URskkb/ayc C3X8oAbXIb9sZ8tUpwZh+x8B93TRIB+4iuhxerYgkBHmCvRQgjolzyFPXg4LVAfCT3FD ofrejLlkUpxES+F7CPgl2ay79kkWxB+K3qVzdEUdZEa8UmwPM8BtrJic5P7/ZlVrYBzT +Lqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684501002; x=1687093002; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=0jD85a1byx0I7vZDl4DIHafULFBs2J0mGqz+tke9Mq8=; b=Q6HJN5C7aCNMeL+ppj5smH6Dpsijjls0Cz/s4oZtsNBFu4NDPVA481cfA1eqyeZUGw cFQ3AB4ab7NcgTRG3L9Ni90oOnx60M0tBbVeOHxWznYfHjOUyC3MUxE3BQaiPNrcDxAZ 0QA6xnF9NDEZ27DxhYkdXLPS/GdHbhCLAl1KFVWVwW+M2mCw8KD1EgYFUjD1xm8wM4WJ JF3t2hKTOjS5RXH498zpijsW0cQuKpJ9qb3/vn5+IrBLi2SCrVfGWCyVVhk2tHYuLDrn WVcZhcKNZgzY7Ga9mwOt1bt4ZFp7/QkK9rqwj20eTcU6Ke9Y4rXZiHamw027rW2PfHFH AA7Q== X-Gm-Message-State: AC+VfDys0OqJ1FYEv4/pixk/JOP7uzX2qi4aAP6GYexSgwOOYjI+aRSM LcoeZRL2gCavDsI+k2KZZPpgwA== X-Google-Smtp-Source: ACHHUZ7qLBaMqtEFsoVZytSwaFeZLiVsaf4BJWwpaPVzvPV/1D/ebboGmUK9N+M9/udAysn5XO2Rlw== X-Received: by 2002:a5d:4cd1:0:b0:307:8d93:a47f with SMTP id c17-20020a5d4cd1000000b003078d93a47fmr1612108wrt.55.1684501001914; Fri, 19 May 2023 05:56:41 -0700 (PDT) Received: from hades (ppp176092130041.access.hol.gr. [176.92.130.41]) by smtp.gmail.com with ESMTPSA id j17-20020a5d4531000000b002ffbf2213d4sm5261492wra.75.2023.05.19.05.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 05:56:41 -0700 (PDT) Date: Fri, 19 May 2023 15:56:39 +0300 From: Ilias Apalodimas To: Abdellatif El Khlifi Cc: Drew.Reed@arm.com, achin.gupta@arm.com, jens.wiklander@linaro.org, nd@arm.com, robh@kernel.org, sjg@chromium.org, trini@konsulko.com, u-boot@lists.denx.de, xueliang.zhong@arm.com Subject: Re: [PATCH v12 01/10] arm64: smccc: add support for SMCCCv1.2 x0-x17 registers Message-ID: References: <20230412094245.44674-1-abdellatif.elkhlifi@arm.com> <20230512121044.111574-1-abdellatif.elkhlifi@arm.com> <20230512121044.111574-2-abdellatif.elkhlifi@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230512121044.111574-2-abdellatif.elkhlifi@arm.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri, May 12, 2023 at 01:10:35PM +0100, Abdellatif El Khlifi wrote: > add support for x0-x17 registers used by the SMC calls > > In SMCCC v1.2 [1] arguments are passed in registers x1-x17. > Results are returned in x0-x17. > > This work is inspired from the following kernel commit: > > arm64: smccc: Add support for SMCCCv1.2 extended input/output registers > > [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= > > Signed-off-by: Abdellatif El Khlifi > Reviewed-by: Jens Wiklander > Reviewed-by: Simon Glass > Cc: Tom Rini > Cc: Simon Glass > Cc: Ilias Apalodimas > > --- > > Changelog: > =============== > > v9: > > * update the copyright string > > v7: > > * improve indentation of ARM_SMCCC_1_2_REGS_Xn_OFFS > > v4: > > * rename the commit title and improve description > new commit title: the current > > v3: > > * port x0-x17 registers support from linux kernel as defined by SMCCCv1.2 > commit title: > arm64: smccc: add Xn registers support used by SMC calls > > arch/arm/cpu/armv8/smccc-call.S | 57 ++++++++++++++++++++++++++++++++- > arch/arm/lib/asm-offsets.c | 16 +++++++++ > include/linux/arm-smccc.h | 45 ++++++++++++++++++++++++++ > 3 files changed, 117 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S > index dc92b28777..93f66d3366 100644 > --- a/arch/arm/cpu/armv8/smccc-call.S > +++ b/arch/arm/cpu/armv8/smccc-call.S > @@ -1,7 +1,11 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > * Copyright (c) 2015, Linaro Limited > - */ > + * Copyright 2022-2023 Arm Limited and/or its affiliates > + * > + * Authors: > + * Abdellatif El Khlifi > +*/ > #include > #include > #include > @@ -45,3 +49,54 @@ ENDPROC(__arm_smccc_smc) > ENTRY(__arm_smccc_hvc) > SMCCC hvc > ENDPROC(__arm_smccc_hvc) > + > +#ifdef CONFIG_ARM64 > + > + .macro SMCCC_1_2 instr > + /* Save `res` and free a GPR that won't be clobbered */ > + stp x1, x19, [sp, #-16]! > + > + /* Ensure `args` won't be clobbered while loading regs in next step */ > + mov x19, x0 > + > + /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */ > + ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] > + ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] > + ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] > + ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] > + ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] > + ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] > + ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] > + ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] > + ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] > + > + \instr #0 > + > + /* Load the `res` from the stack */ > + ldr x19, [sp] > + > + /* Store the registers x0 - x17 into the result structure */ > + stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] > + stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] > + stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] > + stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] > + stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] > + stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] > + stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] > + stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] > + stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] > + > + /* Restore original x19 */ > + ldp xzr, x19, [sp], #16 > + ret > + .endm > + > +/* > + * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, > + * struct arm_smccc_1_2_regs *res); > + */ > +ENTRY(arm_smccc_1_2_smc) > + SMCCC_1_2 smc > +ENDPROC(arm_smccc_1_2_smc) > + > +#endif > diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c > index 6de0ce9152..181a8ac4c2 100644 > --- a/arch/arm/lib/asm-offsets.c > +++ b/arch/arm/lib/asm-offsets.c > @@ -9,6 +9,11 @@ > * generate asm statements containing #defines, > * compile this file to assembler, and then extract the > * #defines from the assembly-language output. > + * > + * Copyright 2022-2023 Arm Limited and/or its affiliates > + * > + * Authors: > + * Abdellatif El Khlifi > */ > > #include > @@ -90,6 +95,17 @@ int main(void) > DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); > DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); > DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); > +#ifdef CONFIG_ARM64 > + DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0)); > + DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2)); > + DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4)); > + DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6)); > + DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8)); > + DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10)); > + DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12)); > + DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14)); > + DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16)); > +#endif > #endif > > return 0; > diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h > index e1d09884a1..f44e9e8f93 100644 > --- a/include/linux/arm-smccc.h > +++ b/include/linux/arm-smccc.h > @@ -1,6 +1,10 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > * Copyright (c) 2015, Linaro Limited > + * Copyright 2022-2023 Arm Limited and/or its affiliates > + * > + * Authors: > + * Abdellatif El Khlifi > */ > #ifndef __LINUX_ARM_SMCCC_H > #define __LINUX_ARM_SMCCC_H > @@ -70,6 +74,47 @@ struct arm_smccc_res { > unsigned long a3; > }; > > +#ifdef CONFIG_ARM64 > +/** > + * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call > + * @a0-a17 argument values from registers 0 to 17 > + */ > +struct arm_smccc_1_2_regs { > + unsigned long a0; > + unsigned long a1; > + unsigned long a2; > + unsigned long a3; > + unsigned long a4; > + unsigned long a5; > + unsigned long a6; > + unsigned long a7; > + unsigned long a8; > + unsigned long a9; > + unsigned long a10; > + unsigned long a11; > + unsigned long a12; > + unsigned long a13; > + unsigned long a14; > + unsigned long a15; > + unsigned long a16; > + unsigned long a17; > +}; > + > +/** > + * arm_smccc_1_2_smc() - make SMC calls > + * @args: arguments passed via struct arm_smccc_1_2_regs > + * @res: result values via struct arm_smccc_1_2_regs > + * > + * This function is used to make SMC calls following SMC Calling Convention > + * v1.2 or above. The content of the supplied param are copied from the > + * structure to registers prior to the SMC instruction. The return values > + * are updated with the content from registers on return from the SMC > + * instruction. > + */ > +asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, > + struct arm_smccc_1_2_regs *res); > +#endif > + > /** > * struct arm_smccc_quirk - Contains quirk information > * @id: quirk identification > -- > 2.25.1 > Reviewed-by: Ilias Apalodimas