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Date: Mon, 24 Jul 2023 05:15:20 +0000
From: Leo Liang <ycliang@andestech.com>
To: Hal Feng <hal.feng@starfivetech.com>
CC: Lukasz Majewski <lukma@denx.de>, Sean Anderson <seanga2@gmail.com>, "Rick
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 Renner Berthing" <emil.renner.berthing@canonical.com>, Xingyu Wu
 <xingyu.wu@starfivetech.com>, <u-boot@lists.denx.de>
Subject: Re: [PATCH v1 3/5] riscv: dts: jh7110: Add clock source from PLL
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References: <20230707105011.129241-1-hal.feng@starfivetech.com>
 <20230707105011.129241-4-hal.feng@starfivetech.com>
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On Fri, Jul 07, 2023 at 06:50:09PM +0800, Hal Feng wrote:
> From: Xingyu Wu <xingyu.wu@starfivetech.com>
> 
> Change the PLL clock source from syscrg to sys_syscon child node.
> 
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 +++---
>  arch/riscv/dts/jh7110-u-boot.dtsi                | 1 -
>  arch/riscv/dts/jh7110.dtsi                       | 8 ++++++--
>  3 files changed, 9 insertions(+), 6 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>