From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1104C001E0 for ; Tue, 25 Jul 2023 22:16:34 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AEFAF86778; Wed, 26 Jul 2023 00:16:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=dolcini.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id F11D086789; Wed, 26 Jul 2023 00:16:30 +0200 (CEST) Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4F8578676D for ; Wed, 26 Jul 2023 00:16:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=dolcini.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=francesco@dolcini.it Received: from francesco-nb.int.toradex.com (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 1178C2062B; Wed, 26 Jul 2023 00:16:27 +0200 (CEST) Date: Wed, 26 Jul 2023 00:16:21 +0200 From: Francesco Dolcini To: Nishanth Menon Cc: Tom Rini , Neha Malcom Francis , Bryan Brattlof , Praneeth Bajjuri , Andrew Davis , Robert Nelson , Vignesh R , u-boot@lists.denx.de Subject: Re: [PATCH 3/6] board: ti: am62x: Add basic initialization for usb voltage, 32k crystal, debounce Message-ID: References: <20230725185253.2123433-1-nm@ti.com> <20230725185253.2123433-4-nm@ti.com> <20230725212504.GH3630934@bill-the-cat> <20230725213755.kc6qcvmkmt2yzzqz@perfected> <20230725214210.GL3630934@bill-the-cat> <20230725220328.fruxsldln7o5geil@tassel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230725220328.fruxsldln7o5geil@tassel> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Tue, Jul 25, 2023 at 05:03:28PM -0500, Nishanth Menon wrote: > On 17:42-20230725, Tom Rini wrote: > > On Tue, Jul 25, 2023 at 04:37:55PM -0500, Nishanth Menon wrote: > > > On 17:25-20230725, Tom Rini wrote: > > > > On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote: > > > [..] > > > > > > > > + /* Set USB0 PHY core voltage to 0.85V */ > > > > > + val = readl(CTRLMMR_USB0_PHY_CTRL); > > > > > + val &= ~(CORE_VOLTAGE); > > > > > + writel(val, CTRLMMR_USB0_PHY_CTRL); > > > > > + > > > > > + /* Set USB1 PHY core voltage to 0.85V */ > > > > > + val = readl(CTRLMMR_USB1_PHY_CTRL); > > > > > + val &= ~(CORE_VOLTAGE); > > > > > + writel(val, CTRLMMR_USB1_PHY_CTRL); > > > > > + > > > > > + /* We have 32k crystal, so lets enable it */ > > > > > + val = readl(MCU_CTRL_LFXOSC_CTRL); > > > > > + val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); > > > > > + writel(val, MCU_CTRL_LFXOSC_CTRL); > > > > > + /* Add any TRIM needed for the crystal here.. */ > > > > > + /* Make sure to mux up to take the SoC 32k from the crystal */ > > > > > + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, > > > > > + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); > > > > > + > > > > > + /* Setup debounce conf registers - arbitrary values. Times are approx */ > > > > > + /* 1.9ms debounce @ 32k */ > > > > > + writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); > > > > > + /* 5ms debounce @ 32k */ > > > > > + writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); > > > > > + /* 20ms debounce @ 32k */ > > > > > + writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); > > > > > + /* 46ms debounce @ 32k */ > > > > > + writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); > > > > > + /* 100ms debounce @ 32k */ > > > > > + writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); > > > > > + /* 156ms debounce @ 32k */ > > > > > + writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); > > > > > + > > > > > video_setup(); > > > > > enable_caches(); > > > > > if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP)) > > > > > > > > Here's a whole lot of seemingly board specific code in a function and > > > > file that's supposed to support any am62 platform. Is this really what > > > > we need, where we need it? > > > > > > * without using the correct voltage for USB, we risk damaging the IOs - > > > board specific, sure. > > > > So what happens when we do this on the other EVM, does it have the same > > values? Is there some must-always-be-safe values? Or is the answer "we > > must do this board specific to be safe" and so need to re-think what can > > and can't be shared between board builds. > > At least the ones we have currently (I am not sure about toradex, > phytech etc), seem to operate the vdd_core at 0.85V .. (which is what > USB is dependent upon). For Toradex, we do have the equivalent code in our board file, see https://git.toradex.com/cgit/u-boot-toradex.git/tree/board/toradex/verdin-am62/verdin-am62.c?h=toradex_ti-u-boot-2023.04#n92 The 32kHz configuration is just different for us, we do not re-use the same you have here. The debounce conf registers I have no idea what they are about, something we should have also on our board? Any additional details? Francesco