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Date: Wed, 9 Aug 2023 15:04:16 +0800
From: Leo Liang <ycliang@andestech.com>
To: Minda Chen <minda.chen@starfivetech.com>
CC: Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>, Rick Chen
 <rick@andestech.com>, Torsten Duwe <duwe@suse.de>, Bin Meng
 <bmeng.cn@gmail.com>, <u-boot@lists.denx.de>, Mason Huo
 <mason.huo@starfivetech.com>
Subject: Re: [RESEND, v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable
 SYS_CACHELINE_SIZE
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References: <20230807085338.27119-1-minda.chen@starfivetech.com>
 <20230807085338.27119-4-minda.chen@starfivetech.com>
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On Mon, Aug 07, 2023 at 04:53:37PM +0800, Minda Chen wrote:
> Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
> SYS_CACHE_SHIFT_6 to enable it.
> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
>  arch/riscv/cpu/jh7110/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>