From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E79D3C83F2C for ; Mon, 4 Sep 2023 06:25:54 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 11B8F86828; Mon, 4 Sep 2023 08:25:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 74404867F7; Mon, 4 Sep 2023 08:25:51 +0200 (CEST) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9A395867F7 for ; Mon, 4 Sep 2023 08:25:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3846PVGX007425; Mon, 4 Sep 2023 14:25:31 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02 (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 4 Sep 2023 14:25:27 +0800 Date: Mon, 4 Sep 2023 14:24:30 +0800 From: Leo Liang To: Shengyu Qu CC: , , , , , , , , , , , , Subject: Re: [PATCH v6 3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT Message-ID: References: <20230824162521.22240-1-wiagn233@outlook.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.10 (e0e92c31) (2023-03-25) X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3846PVGX007425 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri, Aug 25, 2023 at 12:25:20AM +0800, Shengyu Qu wrote: > Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error > would be triggered. Currently, we use DDR ram for SPL malloc arena on > Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as > SPL malloc arena. To avoid triggering ECC error in this scenario, we > imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. > > Signed-off-by: Bo Gan > Signed-off-by: Shengyu Qu > --- > arch/riscv/cpu/jh7110/Kconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang