From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1CA2C83F33 for ; Mon, 4 Sep 2023 05:59:14 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 77EF0864F5; Mon, 4 Sep 2023 07:59:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 987CD867F7; Mon, 4 Sep 2023 07:59:11 +0200 (CEST) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E7D90864D8 for ; Mon, 4 Sep 2023 07:59:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3845w8Rd086709; Mon, 4 Sep 2023 13:58:08 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02 (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 4 Sep 2023 13:58:04 +0800 Date: Mon, 4 Sep 2023 13:57:08 +0800 From: Leo Liang To: Torsten Duwe CC: Rick Chen , Yanhong Wang , Xingyu Wu , Mason Huo , Hal Feng , Simon Glass , Subject: Re: [PATCH 1/2] riscv: allow riscv timer to be instantiated via device tree Message-ID: References: <20230814160404.9B2E067373@verein.lst.de> <20230814160528.4979467373@verein.lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230814160528.4979467373@verein.lst.de> User-Agent: Mutt/2.2.10 (e0e92c31) (2023-03-25) X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3845w8Rd086709 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Mon, Aug 14, 2023 at 06:05:28PM +0200, Torsten Duwe wrote: > For the architectural timer on riscv, there already is a defined > device tree binding[1]. Allow timer instances to be created from > device tree matches, but for now retain the old mechanism, which > registers the timer biggy-back with the CPU. > > [1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml > > Signed-off-by: Torsten Duwe > --- > drivers/timer/riscv_timer.c | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) Reviewed-by: Leo Yu-Chi Liang