[PULL] u-boot-riscv/master

Leo Liang
2021-05-14T11:10:10Z

Hi Tom,

CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504

The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9:

Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 13:09:14 -0400)

are available in the Git repository at:

https://source.denx.de/u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21:

Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 +0800)

----------------------------------------------------------------
Bin Meng (1):
Revert "riscv: cpu: fu740: clear feature disable CSR"

Rick Chen (1):
MAINTAINERS: Add a co-maintainer for RISC-V

Sean Anderson (11):
clk: Warn on failure to assign rate
clk: k210: Fix PLLs not being enabled
clk: k210: Fix PLL enable always getting taken
clk: k210: Remove k210_register_pll
clk: k210: Move the clint clock to under aclk
clk: Add support for the k210 clock driver pre-relocation
riscv: Enable some devices pre-relocation
riscv: Enable AI ram on K210
riscv: k210: Rename airam to aisram
riscv: k210: Use AI as the parent clock of aisram, not PLL1
riscv: Don't reserve AI ram in k210 dts

Vincent Chen (1):
pwm: sifive: make set_config() and set_enable() work properly

MAINTAINERS | 1 +
arch/riscv/cpu/fu540/spl.c | 15 ---------------
arch/riscv/dts/k210.dtsi | 22 +++++++---------------
board/sipeed/maix/maix.c | 14 ++++++++++++--
configs/sipeed_maix_bitm_defconfig | 2 ++
drivers/clk/clk-uclass.c | 11 +++++++----
drivers/clk/kendryte/clk.c | 26 ++++++++++++++------------
drivers/clk/kendryte/pll.c | 26 ++++----------------------
drivers/pwm/pwm-sifive.c | 21 +++++++++++----------
include/configs/sipeed-maix.h | 3 +--
include/kendryte/pll.h | 4 ----
11 files changed, 59 insertions(+), 86 deletions(-)

Best regards,
Leo