[PULL] u-boot-riscv/master

Bin Meng
2021-05-14T12:23:58Z

Hi Leo,

On Fri, May 14, 2021 at 7:10 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Tom,
>
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7504
>
> The following changes since commit 530c8d4af2e18c6142ab7cac6f11dd92c02b2bc9:
>
> Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application' (2021-05-13 13:09:14 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21:
>
> Revert "riscv: cpu: fu740: clear feature disable CSR" (2021-05-14 16:26:20 +0800)
>
> ----------------------------------------------------------------
> Bin Meng (1):
> Revert "riscv: cpu: fu740: clear feature disable CSR"

The following patches are not applied. Without them, SiFive Unleashed
is still not bootable.

http://patchwork.ozlabs.org/project/uboot/patch/20210511120412.25065-1-bmeng.cn at gmail.com/
http://patchwork.ozlabs.org/project/uboot/list/?series=243574

Could you please apply ASAP?

Regards,
Bin