[PATCH 1/1] cmd/exception: test RISC-V 16 bit aligned instruction

[PATCH 1/1] cmd/exception: test RISC-V 16 bit aligned instruction

[Heinrich Schuchardt]

A 16 bit aligned instruction should generated an exception if the C
extension is not available.

Provide an 'extension ialign16' command for testing exception handling.

For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with

    qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false

    => exception ialign16
    Unhandled exception: Instruction address misaligned
    EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
    EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted

    Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 cmd/riscv/exception.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index db8d8af048..f38f454a0b 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -24,6 +24,19 @@ static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc,
 	return CMD_RET_FAILURE;
 }
 
+static int do_ialign16(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	asm volatile (
+		/* jump skipping 2 bytes */
+		".long 0x0060006f\n"
+		".long 0x006f0000\n"
+		".long 0x00000060\n"
+	);
+	printf("The system supports 16 bit aligned instructions.\n");
+	return CMD_RET_SUCCESS;
+}
+
 static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
 			char *const argv[])
 {
@@ -48,6 +61,8 @@ static struct cmd_tbl cmd_sub[] = {
 			 "", ""),
 	U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak,
 			 "", ""),
+	U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16,
+			 "", ""),
 	U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
 			 "", ""),
 	U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
@@ -59,6 +74,7 @@ static char exception_help_text[] =
 	"  The following exceptions are available:\n"
 	"  compressed - compressed instruction\n"
 	"  ebreak     - breakpoint\n"
+	"  ialign16   - 16 bit aligned instruction\n"
 	"  undefined  - illegal instruction\n"
 	"  unaligned  - load address misaligned\n"
 	;
-- 
2.40.1

Re: [PATCH 1/1] cmd/exception: test RISC-V 16 bit aligned instruction

[Leo Liang]

On Thu, Sep 21, 2023 at 12:39:29PM +0200, Heinrich Schuchardt wrote:
> A 16 bit aligned instruction should generated an exception if the C
> extension is not available.
> 
> Provide an 'extension ialign16' command for testing exception handling.
> 
> For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
> and run with
> 
>     qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
> 
>     => exception ialign16
>     Unhandled exception: Instruction address misaligned
>     EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
>     EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted
> 
>     Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
>  cmd/riscv/exception.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>