From: Leo Liang <ycliang@andestech.com>
To: Randolph <randolph@andestech.com>
Cc: <u-boot@lists.denx.de>, <randolph.sklin@gmail.com>,
<dylan@andestech.com>, <tim609@andestech.com>,
<peterlin@andestech.com>
Subject: Re: [PATCH] riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy
Date: Tue, 17 Oct 2023 14:50:15 +0800 [thread overview]
Message-ID: <ZS4upw4jI_-Ihg2B@swlinux02> (raw)
In-Reply-To: <20231012053534.2859887-1-randolph@andestech.com>
On Thu, Oct 12, 2023 at 01:35:34PM +0800, Randolph wrote:
> Source hart information is not necessary in IPI, so we could
> use single-bit-per-hart strategy to rearrange PLICSW mapping.
>
> Bit 0 of Interrupt Pending Bits is hardwired to 0.
> Therefore, we use bit 1 to send IPI to hart 0,
> bit 2 to hart 1, ..., and so on.
>
> Signed-off-by: Randolph <randolph@andestech.com>
> ---
> arch/riscv/lib/andes_plicsw.c | 24 +++++++++++-------------
> 1 file changed, 11 insertions(+), 13 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2023-10-17 6:53 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-12 5:35 [PATCH] riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy Randolph
2023-10-17 6:50 ` Leo Liang [this message]
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