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From: Leo Liang <ycliang@andestech.com>
To: Samuel Holland <samuel@sholland.org>
Cc: Rick Chen <rick@andestech.com>, <u-boot@lists.denx.de>,
	Madushan Nishantha <jlmadushan@gmail.com>
Subject: Re: [PATCH] riscv: Align the trap handler to 64 bytes
Date: Wed, 1 Nov 2023 13:34:50 +0800	[thread overview]
Message-ID: <ZUHjevQxFRimUeXS@swlinux02> (raw)
In-Reply-To: <20231031053603.64062-1-samuel@sholland.org>

On Tue, Oct 31, 2023 at 12:35:41AM -0500, Samuel Holland wrote:
> This is required on CPUs which always operate in CLIC mode, such as the
> T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
> trap vector base address held in mtvec is constrained to be aligned on a
> 64-byte or larger power-of-two boundary."
> 
> Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  arch/riscv/cpu/mtrap.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

      reply	other threads:[~2023-11-01  5:38 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-31  5:35 [PATCH] riscv: Align the trap handler to 64 bytes Samuel Holland
2023-11-01  5:34 ` Leo Liang [this message]

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