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* [PATCH] riscv: Align the trap handler to 64 bytes
@ 2023-10-31  5:35 Samuel Holland
  2023-11-01  5:34 ` Leo Liang
  0 siblings, 1 reply; 2+ messages in thread
From: Samuel Holland @ 2023-10-31  5:35 UTC (permalink / raw)
  To: Rick Chen, Leo; +Cc: u-boot, Samuel Holland, Madushan Nishantha

This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/riscv/cpu/mtrap.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index 6eb3ed1d5a8..5cad7b41ff7 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -26,7 +26,7 @@
 	.text
 
 	/* trap entry */
-	.align 2
+	.align 6
 	.global trap_entry
 trap_entry:
 	addi sp, sp, -32 * REGBYTES
-- 
2.41.0


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2023-10-31  5:35 [PATCH] riscv: Align the trap handler to 64 bytes Samuel Holland
2023-11-01  5:34 ` Leo Liang

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