* [PATCH] riscv: Weakly define invalidate_icache_range()
@ 2023-10-31 5:37 Samuel Holland
2023-11-01 5:35 ` Leo Liang
0 siblings, 1 reply; 2+ messages in thread
From: Samuel Holland @ 2023-10-31 5:37 UTC (permalink / raw)
To: Rick Chen, Leo; +Cc: u-boot, Samuel Holland
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/riscv/lib/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index c46b49eb0ac..afad7e117f3 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end)
{
}
-void invalidate_icache_range(unsigned long start, unsigned long end)
+__weak void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the
--
2.41.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] riscv: Weakly define invalidate_icache_range()
2023-10-31 5:37 [PATCH] riscv: Weakly define invalidate_icache_range() Samuel Holland
@ 2023-11-01 5:35 ` Leo Liang
0 siblings, 0 replies; 2+ messages in thread
From: Leo Liang @ 2023-11-01 5:35 UTC (permalink / raw)
To: Samuel Holland; +Cc: Rick Chen, u-boot
On Tue, Oct 31, 2023 at 12:37:20AM -0500, Samuel Holland wrote:
> Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
> vendor-specific way to invalidate a portion of the instruction cache.
> Allow them to override invalidate_icache_range().
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>
> arch/riscv/lib/cache.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-10-31 5:37 [PATCH] riscv: Weakly define invalidate_icache_range() Samuel Holland
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