[GIT PULL] u-boot-riscv/master

[Leo Liang <ycliang@andestech.com>]

Hi Tom,

The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4:

  Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 09:44:33 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0:

  configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407
----------------------------------------------------------------

+ CI: Use OpenSBI 1.3.1 release for testing
+ riscv: Support resume after exception
+ rng: Support RNG provided by RISC-V Zkr ISA extension
+ board: starfive VF2: Support jtag
+ board: starfive VF2: Support TRNG driver
+ board: sifive unmatched: Move kernel load address

----------------------------------------------------------------
Chanho Park (7):
      riscv: cpu: jh7110: Add gpio helper macros
      board: starfive: spl: Support jtag for VisionFive2 board
      riscv: import read/write_relaxed functions
      clk: starfive: jh7110: Add security clocks
      rng: Add StarFive JH7110 RNG driver
      riscv: dts: jh7110: Add rng device tree node
      configs: visionfive2: Enable JH7110 RNG driver

Heinrich Schuchardt (3):
      CI: use OpenSBI 1.3.1 for testing
      riscv: allow resume after exception
      rng: Provide a RNG based on the RISC-V Zkr ISA extension

Samuel Holland (3):
      riscv: Sort target configs alphabetically
      riscv: Align the trap handler to 64 bytes
      riscv: Weakly define invalidate_icache_range()

Yong-Xuan Wang (1):
      board: sifive: unmatched: move kernel load address to 0x80200000

 .azure-pipelines.yml                      |   8 +-
 .gitlab-ci.yml                            |   8 +-
 arch/riscv/Kconfig                        |  18 +-
 arch/riscv/cpu/mtrap.S                    |   2 +-
 arch/riscv/dts/jh7110.dtsi                |  10 ++
 arch/riscv/include/asm/arch-jh7110/gpio.h |  85 +++++++++
 arch/riscv/include/asm/io.h               |  45 +++++
 arch/riscv/lib/cache.c                    |   2 +-
 arch/riscv/lib/interrupts.c               |  13 ++
 board/starfive/visionfive2/spl.c          |  23 +++
 configs/starfive_visionfive2_defconfig    |   2 +
 doc/api/index.rst                         |   1 +
 doc/api/interrupt.rst                     |   6 +
 drivers/clk/starfive/clk-jh7110.c         |  10 ++
 drivers/rng/Kconfig                       |  14 ++
 drivers/rng/Makefile                      |   2 +
 drivers/rng/jh7110_rng.c                  | 274 ++++++++++++++++++++++++++++++
 drivers/rng/riscv_zkr_rng.c               | 116 +++++++++++++
 include/configs/sifive-unmatched.h        |   2 +-
 include/interrupt.h                       |  45 +++++
 20 files changed, 666 insertions(+), 20 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h
 create mode 100644 doc/api/interrupt.rst
 create mode 100644 drivers/rng/jh7110_rng.c
 create mode 100644 drivers/rng/riscv_zkr_rng.c
 create mode 100644 include/interrupt.h

 Best regards,
 Leo