public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed
* [GIT PULL] u-boot-riscv/master
@ 2023-11-02 10:49 Leo Liang
  2023-11-02 14:53 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2023-11-02 10:49 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4:

  Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01 09:44:33 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0:

  configs: visionfive2: Enable JH7110 RNG driver (2023-11-02 17:45:53 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18407
----------------------------------------------------------------

+ CI: Use OpenSBI 1.3.1 release for testing
+ riscv: Support resume after exception
+ rng: Support RNG provided by RISC-V Zkr ISA extension
+ board: starfive VF2: Support jtag
+ board: starfive VF2: Support TRNG driver
+ board: sifive unmatched: Move kernel load address

----------------------------------------------------------------
Chanho Park (7):
      riscv: cpu: jh7110: Add gpio helper macros
      board: starfive: spl: Support jtag for VisionFive2 board
      riscv: import read/write_relaxed functions
      clk: starfive: jh7110: Add security clocks
      rng: Add StarFive JH7110 RNG driver
      riscv: dts: jh7110: Add rng device tree node
      configs: visionfive2: Enable JH7110 RNG driver

Heinrich Schuchardt (3):
      CI: use OpenSBI 1.3.1 for testing
      riscv: allow resume after exception
      rng: Provide a RNG based on the RISC-V Zkr ISA extension

Samuel Holland (3):
      riscv: Sort target configs alphabetically
      riscv: Align the trap handler to 64 bytes
      riscv: Weakly define invalidate_icache_range()

Yong-Xuan Wang (1):
      board: sifive: unmatched: move kernel load address to 0x80200000

 .azure-pipelines.yml                      |   8 +-
 .gitlab-ci.yml                            |   8 +-
 arch/riscv/Kconfig                        |  18 +-
 arch/riscv/cpu/mtrap.S                    |   2 +-
 arch/riscv/dts/jh7110.dtsi                |  10 ++
 arch/riscv/include/asm/arch-jh7110/gpio.h |  85 +++++++++
 arch/riscv/include/asm/io.h               |  45 +++++
 arch/riscv/lib/cache.c                    |   2 +-
 arch/riscv/lib/interrupts.c               |  13 ++
 board/starfive/visionfive2/spl.c          |  23 +++
 configs/starfive_visionfive2_defconfig    |   2 +
 doc/api/index.rst                         |   1 +
 doc/api/interrupt.rst                     |   6 +
 drivers/clk/starfive/clk-jh7110.c         |  10 ++
 drivers/rng/Kconfig                       |  14 ++
 drivers/rng/Makefile                      |   2 +
 drivers/rng/jh7110_rng.c                  | 274 ++++++++++++++++++++++++++++++
 drivers/rng/riscv_zkr_rng.c               | 116 +++++++++++++
 include/configs/sifive-unmatched.h        |   2 +-
 include/interrupt.h                       |  45 +++++
 20 files changed, 666 insertions(+), 20 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h
 create mode 100644 doc/api/interrupt.rst
 create mode 100644 drivers/rng/jh7110_rng.c
 create mode 100644 drivers/rng/riscv_zkr_rng.c
 create mode 100644 include/interrupt.h

 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT,PULL] u-boot-riscv/master
@ 2025-10-16 12:07 Leo Liang
  2025-10-16 17:38 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-10-16 12:07 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick, e, ziyao

Hi Tom,

The following changes since commit 2ba64e303b2706e5c42a6bf982326d632342ca66:

  Merge patch series "fix an7581 panic caused by attempt to support multiple RAM size" (2025-10-15 15:08:27 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 0ab7710a06401f8cac1d49bac5e66d25f3e6e4e1:

  clk: sophgo: Fix a warning about void returns value (2025-10-16 16:44:49 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27926
----------------------------------------------------------------
- Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S" to fix regression
- clk: sophgo: Fix a warning about void returns value
----------------------------------------------------------------
Tom Rini (1):
      clk: sophgo: Fix a warning about void returns value

Yao Zi (1):
      Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"

 arch/riscv/cpu/start.S          | 26 +-------------------------
 drivers/clk/sophgo/clk-common.h |  2 +-
 2 files changed, 2 insertions(+), 26 deletions(-)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-08-12  8:04 Leo Liang
  2025-08-12 15:22 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-08-12  8:04 UTC (permalink / raw)
  To: trini
  Cc: u-boot, ycliang, rick, heinrich.schuchardt, ben.dooks,
	jamie.gibbons, sputnik, michal.simek

Hi Tom,

The following changes since commit acfacf452441d0a659e3afbd55fd6061aa17e647:

  Prepare v2025.10-rc2 (2025-08-11 13:47:46 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to bddcd6bcba081aaaaafe30d1b8f9f3c83f069bde:

  starfive: fix return code of `mac write_eeprom` (2025-08-12 15:34:39 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27348
----------------------------------------------------------------
- Board: mbv: Prepare MBV for CI
- Board: MPFS Icicle Kit cleanup
- Board: Add Andes Voyager board support
- RISCV: Update SYS_BOOTM_LEN to commonly used value
- starfive: fix return code of `mac write_eeprom`
----------------------------------------------------------------
Heinrich Schuchardt (1):
      starfive: fix return code of `mac write_eeprom`

Jamie Gibbons (6):
      configs: microchip_mpfs_icicle: enable CONFIG_OF_BOARD_SETUP
      board: microchip: mpfs_icicle: make use of ft_board_setup()
      mailbox: add PolarFire SoC mailbox driver
      misc: add PolarFire SoC system controller
      board: microchip: mpfs_icicle: enable new driver configs
      board: microchip: mpfs_icicle: update to use system controller

Leo Yu-Chi Liang (6):
      riscv: board: Add Andes Voyager board Kconfig support
      riscv: dts: andes: Add Voyager device tree
      board: MAINTAINERS: Add Voyager board maintainer
      board: andestech: Add Voyager board support
      configs: andes: add Voyager board defconfig
      doc: board: voyager: Add documentation for Voyager

Martin Herren (4):
      riscv: Set SYS_BOOTM_LEN explicitly to 0x800000
      riscv: Set SYS_BOOTM_LEN default to 0x4000000
      riscv: Remove default SYS_BOOTM_LEN from defconfig
      riscv: Increase Microchip Icicle's SYS_BOOTM_LEN

Michal Simek (4):
      xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
      xilinx: mbv: Add missing mmu-type cpu property
      xilinx: mbv: Fix dt properties in interrupt controller node
      xilinx: mbv: Use separate DTB for binman nodes

 arch/riscv/Kconfig                                 |   4 +
 arch/riscv/dts/Makefile                            |   2 +
 arch/riscv/dts/qilai-voyager.dts                   | 227 +++++++++++++++++++++
 arch/riscv/dts/voyager-u-boot.dtsi                 |  52 +++++
 arch/riscv/dts/xilinx-binman.dts                   |  12 ++
 arch/riscv/dts/xilinx-mbv32.dts                    |   8 +-
 arch/riscv/dts/xilinx-mbv64.dts                    |   8 +-
 board/andestech/voyager/Kconfig                    |  44 ++++
 board/andestech/voyager/MAINTAINERS                |   7 +
 board/andestech/voyager/Makefile                   |   6 +
 board/andestech/voyager/voyager.c                  |  71 +++++++
 board/microchip/mpfs_icicle/Kconfig                |   4 +
 board/microchip/mpfs_icicle/mpfs_icicle.c          | 121 ++++++-----
 .../starfive/visionfive2/visionfive2-i2c-eeprom.c  |   8 +-
 board/xilinx/mbv/Kconfig                           |   1 -
 boot/Kconfig                                       |   2 +-
 configs/ae350_rv32_defconfig                       |   1 -
 configs/ae350_rv32_falcon_defconfig                |   1 -
 configs/ae350_rv32_falcon_xip_defconfig            |   1 -
 configs/ae350_rv32_spl_defconfig                   |   1 -
 configs/ae350_rv32_spl_xip_defconfig               |   1 -
 configs/ae350_rv32_xip_defconfig                   |   1 -
 configs/ae350_rv64_defconfig                       |   1 -
 configs/ae350_rv64_falcon_defconfig                |   1 -
 configs/ae350_rv64_falcon_xip_defconfig            |   1 -
 configs/ae350_rv64_spl_defconfig                   |   1 -
 configs/ae350_rv64_spl_xip_defconfig               |   1 -
 configs/ae350_rv64_xip_defconfig                   |   1 -
 configs/ibex-ast2700_defconfig                     |   1 -
 configs/k230_canmv_defconfig                       |   1 +
 configs/microchip_mpfs_icicle_defconfig            |   4 +
 configs/milkv_duo_defconfig                        |   1 -
 configs/qemu-riscv32_defconfig                     |   1 -
 configs/qemu-riscv32_smode_defconfig               |   1 -
 configs/qemu-riscv32_spl_defconfig                 |   1 -
 configs/qemu-riscv64_defconfig                     |   1 -
 configs/qemu-riscv64_smode_defconfig               |   1 -
 configs/qemu-riscv64_spl_defconfig                 |   1 -
 configs/sifive_unleashed_defconfig                 |   1 -
 configs/sifive_unmatched_defconfig                 |   1 -
 configs/sipeed_licheerv_nano_defconfig             |   1 -
 configs/sipeed_maix_bitm_defconfig                 |   1 +
 configs/sipeed_maix_smode_defconfig                |   1 +
 configs/starfive_visionfive2_defconfig             |   1 -
 configs/th1520_lpi4a_defconfig                     |   1 -
 configs/voyager_spl_defconfig                      |  66 ++++++
 configs/xilinx_mbv32_defconfig                     |   2 +
 configs/xilinx_mbv32_smode_defconfig               |   2 +
 configs/xilinx_mbv64_defconfig                     |   2 +
 configs/xilinx_mbv64_smode_defconfig               |   2 +
 doc/board/andestech/index.rst                      |   1 +
 doc/board/andestech/voyager.rst                    |  81 ++++++++
 drivers/mailbox/Kconfig                            |   7 +
 drivers/mailbox/Makefile                           |   1 +
 drivers/mailbox/mpfs-mbox.c                        | 177 ++++++++++++++++
 drivers/misc/Kconfig                               |   9 +
 drivers/misc/Makefile                              |   1 +
 drivers/misc/mpfs_syscontroller.c                  | 157 ++++++++++++++
 include/configs/voyager.h                          |  40 ++++
 include/mpfs-mailbox.h                             |  67 ++++++
 60 files changed, 1121 insertions(+), 103 deletions(-)
 create mode 100644 arch/riscv/dts/qilai-voyager.dts
 create mode 100644 arch/riscv/dts/voyager-u-boot.dtsi
 create mode 100644 arch/riscv/dts/xilinx-binman.dts
 create mode 100644 board/andestech/voyager/Kconfig
 create mode 100644 board/andestech/voyager/MAINTAINERS
 create mode 100644 board/andestech/voyager/Makefile
 create mode 100644 board/andestech/voyager/voyager.c
 create mode 100644 configs/voyager_spl_defconfig
 create mode 100644 doc/board/andestech/voyager.rst
 create mode 100644 drivers/mailbox/mpfs-mbox.c
 create mode 100644 drivers/misc/mpfs_syscontroller.c
 create mode 100644 include/configs/voyager.h
 create mode 100644 include/mpfs-mailbox.h

 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-05-21  9:50 Leo Liang
  2025-05-21 18:39 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-05-21  9:50 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit a3e09b24ffd4429909604f1b28455b44306edbaa:

  Merge tag 'mmc-2025-05-20' of https://source.denx.de/u-boot/custodians/u-boot-mmc (2025-05-20 08:35:31 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to ff6e20c32ff33c6963f7d0a79a0914681461f4fa:

  riscv: dts: th1520: Complete clock tree (2025-05-21 16:49:58 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26259

----------------------------------------------------------------
- Initial SPL support for T-Head TH1520 SoC
- Improve usability of TH1520 with mainline SPL
- Support building RV32 & RV64 images
- riscv: Improve jh7110 support
----------------------------------------------------------------
E Shattow (3):
      riscv: starfive: jh7110: move uart0 clock frequency to config header
      riscv: dts: jh7110: remove redundant parent nodes
      riscv: dts: jh7110: override syscrg assigned clock rates with defaults

Mayuresh Chitale (4):
      riscv: image: Add new image type for RV64
      riscv: Select appropriate image type
      booti/bootm: riscv: Verify image arch type
      riscv: insn-def.h: Fix header guard

Yao Zi (16):
      riscv: dts: binman.dtsi: Drop filename property for proper U-Boot
      riscv: Access gd with inline assembly when building with LTO or Clang
      riscv: lib: Split out support for T-Head cache management operations
      configs: th1520_lpi4a: Add UART clock frequency
      riscv: cpu: Add TH1520 CPU support
      ram: thead: Add initial DDR controller support for TH1520
      riscv: dts: th1520: Preserve necessary devices for SPL
      riscv: dts: lichee-module-4a: Preserve memory node for SPL
      riscv: dts: th1520: Add DRAM controller
      riscv: dts: th1520: Add binman configuration
      board: thead: licheepi4a: Enable SPL support
      doc: thead: lpi4a: Update documentation
      riscv: cpu: th1520: Initialize IOPMPs in SPL
      clk: thead: Port clock controller driver of TH1520 SoC
      riscv: cpu: th1520: Select clock driver
      riscv: dts: th1520: Complete clock tree

 arch/riscv/Kconfig                                 |    9 +
 arch/riscv/cpu/cpu.c                               |    6 +
 arch/riscv/cpu/cv1800b/Kconfig                     |    1 +
 arch/riscv/cpu/cv1800b/Makefile                    |    1 -
 arch/riscv/cpu/th1520/Kconfig                      |   22 +
 arch/riscv/cpu/th1520/Makefile                     |    8 +
 arch/riscv/cpu/th1520/cache.c                      |   32 +
 arch/riscv/cpu/th1520/cpu.c                        |   21 +
 arch/riscv/cpu/th1520/dram.c                       |   21 +
 arch/riscv/cpu/th1520/spl.c                        |   96 ++
 arch/riscv/dts/binman.dtsi                         |   15 +-
 arch/riscv/dts/jh7110-common-u-boot.dtsi           |    1 -
 arch/riscv/dts/jh7110-u-boot.dtsi                  |   73 +-
 arch/riscv/dts/th1520-lichee-module-4a.dtsi        |    9 +-
 arch/riscv/dts/th1520-lichee-pi-4a.dts             |    1 +
 arch/riscv/dts/th1520.dtsi                         |   91 +-
 arch/riscv/dts/thead-th1520-binman.dtsi            |   55 ++
 arch/riscv/include/asm/arch-th1520/cpu.h           |    9 +
 arch/riscv/include/asm/arch-th1520/iopmp.h         |   42 +
 arch/riscv/include/asm/arch-th1520/spl.h           |   10 +
 arch/riscv/include/asm/global_data.h               |   19 +
 arch/riscv/include/asm/insn-def.h                  |    6 +-
 arch/riscv/include/asm/u-boot.h                    |    4 +
 arch/riscv/lib/Makefile                            |    1 +
 arch/riscv/lib/bootm.c                             |    4 +
 .../riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} |    0
 board/thead/th1520_lpi4a/Kconfig                   |    5 +-
 board/thead/th1520_lpi4a/Makefile                  |    1 +
 board/thead/th1520_lpi4a/spl.c                     |   48 +
 boot/image.c                                       |    3 +-
 cmd/booti.c                                        |    7 +-
 common/board_r.c                                   |    4 +-
 common/init/board_init.c                           |    7 +-
 configs/th1520_lpi4a_defconfig                     |   18 +
 doc/board/thead/lpi4a.rst                          |   58 +-
 drivers/clk/Kconfig                                |    1 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/thead/Kconfig                          |   19 +
 drivers/clk/thead/Makefile                         |    5 +
 drivers/clk/thead/clk-th1520-ap.c                  | 1031 ++++++++++++++++++++
 drivers/ram/Kconfig                                |    1 +
 drivers/ram/Makefile                               |    4 +
 drivers/ram/thead/Kconfig                          |    5 +
 drivers/ram/thead/Makefile                         |    1 +
 drivers/ram/thead/th1520_ddr.c                     |  787 +++++++++++++++
 include/configs/starfive-visionfive2.h             |    2 +
 include/configs/th1520_lpi4a.h                     |    1 +
 include/image.h                                    |    3 +-
 48 files changed, 2459 insertions(+), 110 deletions(-)
 create mode 100644 arch/riscv/cpu/th1520/Kconfig
 create mode 100644 arch/riscv/cpu/th1520/Makefile
 create mode 100644 arch/riscv/cpu/th1520/cache.c
 create mode 100644 arch/riscv/cpu/th1520/cpu.c
 create mode 100644 arch/riscv/cpu/th1520/dram.c
 create mode 100644 arch/riscv/cpu/th1520/spl.c
 create mode 100644 arch/riscv/dts/thead-th1520-binman.dtsi
 create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h
 create mode 100644 arch/riscv/include/asm/arch-th1520/iopmp.h
 create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h
 rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%)
 create mode 100644 board/thead/th1520_lpi4a/spl.c
 create mode 100644 drivers/clk/thead/Kconfig
 create mode 100644 drivers/clk/thead/Makefile
 create mode 100644 drivers/clk/thead/clk-th1520-ap.c
 create mode 100644 drivers/ram/thead/Kconfig
 create mode 100644 drivers/ram/thead/Makefile
 create mode 100644 drivers/ram/thead/th1520_ddr.c

 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-04-25 10:07 Leo Liang
  2025-04-25 10:35 ` Yao Zi
                   ` (2 more replies)
  0 siblings, 3 replies; 76+ messages in thread
From: Leo Liang @ 2025-04-25 10:07 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 10f48365112b164bee6564033ab682747efcb483:

  Merge patch series "Add PCIe support for TI AM64 SoC" (2025-04-24 10:46:17 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 5ac699efe94f24df561d33e420d3c73f5fb797e8:

  board: starfive: visionfive2: Order board detection logic to match config (2025-04-25 17:04:09 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/25940
----------------------------------------------------------------
- riscv: lib: Simplify FDT retrieving process
- board: k1: pinctrl: Add pinctrl support for bananapi-f3
- binman: riscv: Fix binman_sym functionality
- board: starfive: visionfive2: Reorder board detection logic
- board: starfive: Add DeepComputing FML13V01 support
----------------------------------------------------------------
E Shattow (2):
      doc: board: starfive: visionfive2: add missing format command to Flashing
      board: starfive: visionfive2: Order board detection logic to match config

Heinrich Schuchardt (9):
      configs: qemu-riscv raise CONFIG_NR_DRAM_BANKS
      configs: add jh7110-deepcomputing-fml13v01 to VF2 defconfig
      riscv: dts: jh7110: add DeepComputing FML13V01 device-tree
      board: starfive: DeepComputing FML13V01 fdt selection
      board: starfive: spl: support DeepComputing FML13V01
      doc: add DeepComputing FML13V01 documentation
      doc: starfive: use consistent formatting
      doc: starfive: use jh7110_common.rst
      doc: jh7110: describe debug UART

Huan Zhou (2):
      riscv: dts: k1: add pinctrl property in dts.
      config: Enable pinctrl in bananapi-f3

Minda Chen (1):
      MAINTAINERS: visionfive2: Add match N: starfive pattern

Yao Zi (7):
      riscv: lib: Add a default implementation of board_fdt_blob_setup
      board: qemu: riscv: Remove duplicated board_fdt_blob_setup
      board: starfive: Remove duplicated board_fdt_blob_setup
      board: sifive: Remove dead board_fdt_blob_setup
      riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot
      riscv: dts: starfive: Prevent binman from relocating symbols in SPL
      riscv: Provide __image_copy_{start_end} symbols in linkerscript

 arch/riscv/cpu/u-boot-spl.lds                      |   2 +
 arch/riscv/cpu/u-boot.lds                          |   3 +
 arch/riscv/dts/binman.dtsi                         |   2 +-
 .../dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi  |   7 ++
 arch/riscv/dts/k1-bananapi-f3.dts                  |   3 +
 arch/riscv/dts/k1-pinctrl.dtsi                     |  19 ++++
 arch/riscv/dts/k1.dtsi                             |   8 +-
 arch/riscv/dts/starfive-visionfive2-binman.dtsi    |   1 +
 arch/riscv/lib/Makefile                            |   1 +
 arch/riscv/lib/board.c                             |  19 ++++
 board/emulation/qemu-riscv/qemu-riscv.c            |   8 --
 board/sifive/unleashed/unleashed.c                 |  11 ---
 board/sifive/unmatched/unmatched.c                 |  10 --
 board/starfive/visionfive2/MAINTAINERS             |   2 +-
 board/starfive/visionfive2/spl.c                   |  43 +++++----
 board/starfive/visionfive2/starfive_visionfive2.c  |  16 +---
 configs/bananapi-f3_defconfig                      |   2 +
 configs/qemu-riscv32_defconfig                     |   1 -
 configs/qemu-riscv32_smode_defconfig               |   1 -
 configs/qemu-riscv32_spl_defconfig                 |   1 -
 configs/qemu-riscv64_defconfig                     |   1 -
 configs/qemu-riscv64_smode_defconfig               |   1 -
 configs/qemu-riscv64_spl_defconfig                 |   1 -
 configs/starfive_visionfive2_defconfig             |   2 +-
 doc/board/starfive/deepcomputing_fml13v01.rst      |  80 ++++++++++++++++
 doc/board/starfive/index.rst                       |   1 +
 doc/board/starfive/jh7110_common.rst               | 103 +++++++++++++++++++++
 doc/board/starfive/milk-v_mars.rst                 |  18 +---
 doc/board/starfive/pine64_star64.rst               |  26 +-----
 doc/board/starfive/visionfive2.rst                 |  48 ++--------
 30 files changed, 292 insertions(+), 149 deletions(-)
 create mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
 create mode 100644 arch/riscv/dts/k1-pinctrl.dtsi
 create mode 100644 arch/riscv/lib/board.c
 create mode 100644 doc/board/starfive/deepcomputing_fml13v01.rst
 create mode 100644 doc/board/starfive/jh7110_common.rst


Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-03-25  6:19 Leo Liang
  2025-03-25 20:18 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-03-25  6:19 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 3d8be1f5ec30180748259a251efe4f63c8b4b329:

  Prepare v2025.05-rc5 (2025-03-24 20:00:24 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to b452ed448fb2ad44a4b0a07908a3673c25beb5d9:

  openpiton: riscv64: Drop unnecessary 'imply SPL_RISCV_MMODE' (2025-03-25 12:13:50 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/25312
----------------------------------------------------------------
- Fix warning
- Fix incorrect return value
----------------------------------------------------------------
Tom Rini (1):
      openpiton: riscv64: Drop unnecessary 'imply SPL_RISCV_MMODE'

Yao Zi (1):
      clk: sophgo: Fix return values of register updating helpers

 board/openpiton/riscv64/Kconfig | 1 -
 drivers/clk/sophgo/clk-common.h | 6 ++++--
 2 files changed, 4 insertions(+), 3 deletions(-)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-03-06 12:18 Leo Liang
  2025-03-07 11:20 ` Yao Zi
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-03-06 12:18 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit 409d37e869e91453d94319792e17d1d882259b49:

  led: Fix next Coverity scan error (2025-03-04 12:07:23 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 6e71966fa8a5e667f53170165b36ee59a1dfc465:

  board: sifive: Remove duplicated board_fdt_blob_setup (2025-03-06 14:09:39 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/25004
----------------------------------------------------------------
- starfive: simplify binman config
- riscv: remove duplicated board_fdt_blob_setup
- spacemit: update k1 uart compatible
- sifive: unmatched: add 'nvme scan' to preboot
----------------------------------------------------------------
Heinrich Schuchardt (5):
      configs: SiFive Unmatched: add 'nvme scan' to preboot
      riscv: dts: add OF_LIST handling to binman.dtsi
      riscv: dts: no default configuration for MULTI_DTB_FIT
      board: starfive: spl: strip off 'starfive/' prefix
      riscv: dts: starfive: remove duplicate itb entries

Junhui Liu (1):
      riscv: dts: spacemit: Update UART compatible for k1

Yao Zi (4):
      riscv: lib: Add a default implementation of board_fdt_blob_setup
      board: qemu: riscv: Remove duplicated board_fdt_blob_setup
      board: starfive: Remove duplicated board_fdt_blob_setup
      board: sifive: Remove duplicated board_fdt_blob_setup

 arch/riscv/dts/binman.dtsi                        | 10 ++-
 arch/riscv/dts/k1.dtsi                            | 22 +++----
 arch/riscv/dts/starfive-visionfive2-binman.dtsi   | 76 -----------------------
 arch/riscv/lib/Makefile                           |  1 +
 arch/riscv/lib/board.c                            | 19 ++++++
 board/emulation/qemu-riscv/qemu-riscv.c           |  8 ---
 board/sifive/unleashed/unleashed.c                | 11 ----
 board/sifive/unmatched/unmatched.c                | 10 ---
 board/starfive/visionfive2/spl.c                  |  4 ++
 board/starfive/visionfive2/starfive_visionfive2.c | 10 ---
 configs/sifive_unmatched_defconfig                |  2 +-
 11 files changed, 43 insertions(+), 130 deletions(-)
 create mode 100644 arch/riscv/lib/board.c

 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-02-20  5:13 Leo Liang
  2025-02-20 17:19 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-02-20  5:13 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 7a45cb4ffeff034304789954bb222ddd7d02104a:

  fs/erofs: fix an integer overflow in symlink resolution (2025-02-18 12:32:07 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 399a03442f0874bd2eecaa22f96a37378dabf390:

  configs: starfive: use LwIP network stack and enable wget command (2025-02-20 12:18:41 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/24692
----------------------------------------------------------------
- board: VisionFive 2: Update maintainer file
- configs: starfive: Add LwIP network and wget command
- configs: microchip: set DEFAULT_FDT_FILE
----------------------------------------------------------------
E Shattow (1):
      configs: starfive: use LwIP network stack and enable wget command

Hal Feng (1):
      board: starfive: Update the maintainer file for VisionFive 2 board

Heinrich Schuchardt (1):
      configs: microchip_mpfs_icicle: set DEFAULT_FDT_FILE

 board/starfive/visionfive2/MAINTAINERS  | 9 ++++-----
 configs/microchip_mpfs_icicle_defconfig | 1 +
 configs/starfive_visionfive2_defconfig  | 3 ++-
 include/configs/microchip_mpfs_icicle.h | 1 +
 4 files changed, 8 insertions(+), 6 deletions(-)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-02-03  8:17 Leo Liang
  2025-02-03 21:26 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-02-03  8:17 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 2b1c8d3b2da46ce0f7108f279f04bc66f1d8d09a:

  cmd: Fix Kconfig coding style (2025-01-31 11:29:05 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to faf237d1b43c3221e78bfa0310833fc5bc71bc21:

  riscv: cpu: jh7110: fallback to generic cleanup_before_linux() (2025-02-03 15:26:06 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/24428

----------------------------------------------------------------
- RISC-V: Add some fixes
- RISC-V: Integrate OP-TEE into the RISC-V boot flow
- RISC-V: Unify implementation of cleanup_before_linux() for RISC-V ports
- RISC-V: cmd: Add bhyve SBI implementation ID
- Board: K1: Probe dram size during boot phase
----------------------------------------------------------------
Hal Feng (1):
      pinctrl: starfive: Correct driver declaration for starfive_gpio

Heinrich Schuchardt (2):
      riscv: AVAILABLE_HARTS is not compatible with XIP
      cmd: sbi: add bhyve SBI implementation ID

Huan Zhou (1):
      riscv: spacemit: k1: probe dram size during boot phase.

Yao Zi (3):
      riscv: add a generic implementation for cleanup_before_linux()
      riscv: cpu: generic: fallback to generic cleanup_before_linux()
      riscv: cpu: jh7110: fallback to generic cleanup_before_linux()

Yu-Chien Peter Lin (2):
      riscv: Add CONFIG_SPL_OPTEE_LOAD_ADDR
      riscv: dts: binman.dtsi: Include OP-TEE OS image

 arch/riscv/Kconfig                          |  7 +++++
 arch/riscv/cpu/cpu.c                        | 17 ++++++++++++
 arch/riscv/cpu/generic/Makefile             |  1 -
 arch/riscv/cpu/generic/cpu.c                | 22 ----------------
 arch/riscv/cpu/jh7110/Makefile              |  1 -
 arch/riscv/cpu/jh7110/cpu.c                 | 23 -----------------
 arch/riscv/cpu/k1/dram.c                    | 40 +++++++++++++++++++++++++++--
 arch/riscv/dts/binman.dtsi                  | 26 +++++++++++++++++--
 cmd/riscv/sbi.c                             |  1 +
 drivers/pinctrl/starfive/pinctrl-starfive.c |  4 +--
 10 files changed, 89 insertions(+), 53 deletions(-)
 delete mode 100644 arch/riscv/cpu/generic/cpu.c
 delete mode 100644 arch/riscv/cpu/jh7110/cpu.c

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2025-01-17  1:53 Leo Liang
  2025-01-17 17:56 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2025-01-17  1:53 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 178f6ecb21fe12ada74a9a1a08093c812b15eea5:

  Merge patch series "bootstd: Support recording images" (2025-01-15 19:27:14 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to b3ce35900cfa500a31fad652302a92cab604d6b5:

  doc: canaan: Add K230 CanMV board (2025-01-16 15:55:27 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/24215
----------------------------------------------------------------
- RISC-V: Add "riscv,isa-extensions" and multi-letter extension parsing support
- RISC-V: Add default cache line size
- Board: Canaan: Add K230-CanMV support
- Board: VisionFive2: Split out target specific configuration
----------------------------------------------------------------
E Shattow (1):
      riscv: dts: starfive: split out visionfive2 target specific configuration

Junhui Liu (5):
      usb: dwc2: Add support for Canaan K230
      riscv: dts: canaan: Add basic device tree for K230 CanMV board
      riscv: cpu: k230: Add support for Canaan Kendryte K230 SoC
      riscv: canaan: k230_canmv: Add initial support
      doc: canaan: Add K230 CanMV board

Mayuresh Chitale (2):
      riscv: Enhance extension probing
      riscv: Fallback to riscv,isa

Yu-Chien Peter Lin (1):
      Kconfig: Add a default cache line size for RISC-V

 arch/Kconfig                                       |   3 +-
 arch/riscv/Kconfig                                 |   5 +
 arch/riscv/cpu/cpu.c                               | 600 +++++++++++++++++++--
 arch/riscv/cpu/k230/Kconfig                        |  14 +
 arch/riscv/cpu/k230/Makefile                       |   6 +
 arch/riscv/cpu/k230/cpu.c                          |   9 +
 arch/riscv/cpu/k230/dram.c                         |  21 +
 arch/riscv/dts/Makefile                            |   1 +
 arch/riscv/dts/jh7110-common-u-boot.dtsi           |  95 ----
 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi       |   1 +
 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi    |   1 +
 .../jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi |   1 +
 .../jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi |   1 +
 arch/riscv/dts/k230-canmv.dts                      |  31 ++
 arch/riscv/dts/k230-u-boot.dtsi                    |  25 +
 arch/riscv/dts/k230.dtsi                           | 175 ++++++
 arch/riscv/dts/starfive-visionfive2-binman.dtsi    | 102 ++++
 arch/riscv/include/asm/cpufeature.h                |  37 ++
 arch/riscv/include/asm/hwcap.h                     | 105 ++++
 arch/riscv/lib/cache.c                             |  26 +-
 board/canaan/k230_canmv/Kconfig                    |  19 +
 board/canaan/k230_canmv/MAINTAINERS                |   6 +
 board/canaan/k230_canmv/Makefile                   |   5 +
 board/canaan/k230_canmv/board.c                    |   9 +
 configs/k230_canmv_defconfig                       |  19 +
 doc/board/canaan/index.rst                         |   8 +
 doc/board/canaan/k230_canmv.rst                    |  88 +++
 doc/board/index.rst                                |   1 +
 doc/device-tree-bindings/usb/dwc2.txt              |   1 +
 29 files changed, 1261 insertions(+), 154 deletions(-)
 create mode 100644 arch/riscv/cpu/k230/Kconfig
 create mode 100644 arch/riscv/cpu/k230/Makefile
 create mode 100644 arch/riscv/cpu/k230/cpu.c
 create mode 100644 arch/riscv/cpu/k230/dram.c
 create mode 100644 arch/riscv/dts/k230-canmv.dts
 create mode 100644 arch/riscv/dts/k230-u-boot.dtsi
 create mode 100644 arch/riscv/dts/k230.dtsi
 create mode 100644 arch/riscv/dts/starfive-visionfive2-binman.dtsi
 create mode 100644 arch/riscv/include/asm/cpufeature.h
 create mode 100644 arch/riscv/include/asm/hwcap.h
 create mode 100644 board/canaan/k230_canmv/Kconfig
 create mode 100644 board/canaan/k230_canmv/MAINTAINERS
 create mode 100644 board/canaan/k230_canmv/Makefile
 create mode 100644 board/canaan/k230_canmv/board.c
 create mode 100644 configs/k230_canmv_defconfig
 create mode 100644 doc/board/canaan/index.rst
 create mode 100644 doc/board/canaan/k230_canmv.rst

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-11-27 13:08 Leo Liang
  2024-11-27 18:54 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-11-27 13:08 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit 3881c6b90350b0b04085ad46ef64989b43967eef:

  configs: Resync with savedefconfig (2024-11-26 08:17:35 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to bdca70632dad38a1f7830c955771c0bd88ce7ae0:

  configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig (2024-11-27 19:58:08 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23592
----------------------------------------------------------------
- some configs modification
----------------------------------------------------------------
Andreas Schwab (1):
      configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE

Heinrich Schuchardt (1):
      configs: SiFive Unmatched: enable 'env erase' sub-command

Yuri Zaporozhets (2):
      spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V
      configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig

 common/spl/Kconfig                     | 1 +
 configs/sifive_unmatched_defconfig     | 2 ++
 configs/starfive_visionfive2_defconfig | 3 +++
 3 files changed, 6 insertions(+)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-11-06 12:12 Leo Liang
  2024-11-08 16:51 ` Tom Rini
  2024-11-11 13:24 ` Tom Rini
  0 siblings, 2 replies; 76+ messages in thread
From: Leo Liang @ 2024-11-06 12:12 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit 56accc56b9aab87ef4809ccc588e1257969cd271:

  bios_emulator: fix first argument of pci_{read,write}_config_* function calls (2024-11-04 18:01:58 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to d5f5e778183d5908caa2954b9438614252b806dd:

  riscv: Introduce configuration for 64bit version Microblaze V (2024-11-06 19:42:54 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23239
----------------------------------------------------------------
- configs: visionfive2 defconfig: re-enable SPL_SYS_MMCSD_RAW_MODE
- driver: sifive ccache: enable TRUNKCLOCKGATE & REGIONCLOCKGATE
- board: support 64bit Microblaze V
----------------------------------------------------------------
Andreas Schwab (1):
      configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE

Michal Simek (3):
      xilinx: mbv: Place DTB by default to DDR location
      xilinx: mbv: Align smode_defconfig with upstream QEMU
      riscv: Introduce configuration for 64bit version Microblaze V

Nick Hu (1):
      driver: sifive ccache: enable TRUNKCLOCKGATE and REGIONCLOCKGATE

 arch/riscv/dts/Makefile                |  1 +
 arch/riscv/dts/xilinx-mbv64.dts        | 99 ++++++++++++++++++++++++++++++++++
 board/xilinx/Kconfig                   |  2 +-
 configs/starfive_visionfive2_defconfig |  3 ++
 configs/xilinx_mbv32_smode_defconfig   | 12 ++---
 configs/xilinx_mbv64_defconfig         | 44 +++++++++++++++
 configs/xilinx_mbv64_smode_defconfig   | 48 +++++++++++++++++
 drivers/cache/cache-sifive-ccache.c    | 33 ++++++++++--
 8 files changed, 232 insertions(+), 10 deletions(-)
 create mode 100644 arch/riscv/dts/xilinx-mbv64.dts
 create mode 100644 configs/xilinx_mbv64_defconfig
 create mode 100644 configs/xilinx_mbv64_smode_defconfig

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-10-29 12:33 Leo Liang
  2024-10-29 16:37 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-10-29 12:33 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit bfdfc6c12e8ca68fff1a7ed3892c180143a6a0ef:

  Revert "acpi_table: Fix coverity defect in acpi_write_spcr" (2024-10-28 20:53:34 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 239e4705099c7516f3d3cf958f3e540d635a4ed3:

  riscv: dts: mpfs: migrate to OF_UPSTREAM (2024-10-29 19:58:22 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23080

----------------------------------------------------------------
- board: migrate PolarFire to use OF_UPSTREAM
- dts: align DT with QEMU amd-microblaze-v-virt platform
- riscv: fix resume utility
----------------------------------------------------------------
Anton Blanchard (1):
      riscv: resume needs to be a global

Conor Dooley (3):
      clk: microchip: mpfs: support new syscon based devicetree configuration
      board: mpfs_icicle: imply new clk driver dependencies
      riscv: dts: mpfs: migrate to OF_UPSTREAM

Michal Simek (1):
      riscv: mbv: Align DT with QEMU

 arch/riscv/dts/Makefile                    |   1 -
 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi |  71 ----
 arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi |  14 -
 arch/riscv/dts/mpfs-icicle-kit.dts         | 208 ------------
 arch/riscv/dts/mpfs.dtsi                   | 511 -----------------------------
 arch/riscv/dts/xilinx-mbv32.dts            |  30 +-
 arch/riscv/include/asm/global_data.h       |   1 +
 arch/riscv/lib/interrupts.c                |  10 +-
 board/microchip/mpfs_icicle/Kconfig        |   2 +
 board/xilinx/mbv/Kconfig                   |   6 +-
 configs/microchip_mpfs_icicle_defconfig    |   4 +-
 configs/xilinx_mbv32_defconfig             |  12 +-
 drivers/clk/microchip/Kconfig              |   2 +
 drivers/clk/microchip/mpfs_clk.c           |  63 +++-
 drivers/clk/microchip/mpfs_clk.h           |   5 +-
 drivers/clk/microchip/mpfs_clk_cfg.c       |  16 +-
 drivers/clk/microchip/mpfs_clk_periph.c    |  37 +--
 dts/upstream/src/riscv/Makefile            |   6 +
 18 files changed, 115 insertions(+), 884 deletions(-)
 delete mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
 delete mode 100644 arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts
 delete mode 100644 arch/riscv/dts/mpfs.dtsi
 create mode 100644 dts/upstream/src/riscv/Makefile

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-10-28 12:24 Leo Liang
  2024-10-28 19:33 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-10-28 12:24 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit 3df6145db0ed3430a2af089db5a82372bea3f4d5:

  x86: Missed removal of CMD_BOOTEFI_HELLO_COMPILE (2024-10-27 20:11:36 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 9e859849e2caa17d730bc4507fd6ef3c7959d3b4:

  riscv: cache: Add CBO instructions (2024-10-28 18:56:54 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23051
----------------------------------------------------------------
- risc-v: Add Zicbom support
- board: Support RVVM board
- DTS: device tree fixes
- configs: Enable some configs
----------------------------------------------------------------
E Shattow (2):
      riscv64: dts: starfive: Star64 ethernet0 phy delay values sync with upstream Linux
      riscv64: dts: starfive: Mars ethernet0 phy delay values sync with upstream Linux

Heinrich Schuchardt (3):
      cmd: sbi: Add FWFT, MPXY extensions
      riscv: add missing linefeed in error message
      configs: visionfive2: enable CONFIG_CMD_ERASEENV

LekKit (3):
      riscv: qemu: Enable booting from NVMe
      riscv: qemu: Enable EFI framebuffer
      riscv: qemu: Explicitly advertise RVVM support

Maksim Kiselev (2):
      gpio: dw: Add ngpios DT-property support
      configs: th1520_lpi4a: Enable CMD_GPIO, DM_GPIO and DWAPB_GPIO driver

Mayuresh Chitale (2):
      riscv: Add support for defining instructions
      riscv: cache: Add CBO instructions

 arch/riscv/Kconfig                     |  6 ++-
 arch/riscv/include/asm/insn-def.h      | 39 ++++++++++++++
 arch/riscv/include/asm/sbi.h           |  4 +-
 arch/riscv/lib/cache.c                 | 96 ++++++++++++++++++++++++++++++++++
 arch/riscv/lib/fdt_fixup.c             |  2 +-
 board/emulation/qemu-riscv/Kconfig     |  2 +
 board/starfive/visionfive2/spl.c       |  6 +--
 cmd/riscv/sbi.c                        |  4 +-
 configs/starfive_visionfive2_defconfig |  1 +
 configs/th1520_lpi4a_defconfig         |  4 +-
 drivers/gpio/dwapb_gpio.c              |  4 +-
 include/configs/qemu-riscv.h           |  1 +
 12 files changed, 159 insertions(+), 10 deletions(-)
 create mode 100644 arch/riscv/include/asm/insn-def.h

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-07-22  8:29 Leo Liang
  2024-07-22 19:31 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-07-22  8:29 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 5024a96db8ea6ff2e814f4599af9e5faf09296b7:

  Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into dts/upstream (2024-07-20 11:15:22 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to dd3cd9eecc9846e7c37a97c9755d2a83fb995cbb:

  Revert "riscv: dts: jh7110: Enable PLL node in SPL" (2024-07-22 15:42:07 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/21724
----------------------------------------------------------------
Andreas Schwab (1):
      board: sifive: unmatched: remove extra space in fdtfile value

Heinrich Schuchardt (2):
      riscv: add RISC-V fields to bdinfo command
      riscv: semihosting: correct alignment

Leo Yu-Chi Liang (1):
      Revert "riscv: dts: jh7110: Enable PLL node in SPL"

 arch/riscv/dts/jh7110-u-boot.dtsi    |  4 ----
 arch/riscv/lib/Makefile              |  1 +
 arch/riscv/lib/bdinfo.c              | 18 ++++++++++++++++++
 arch/riscv/lib/semihosting.S         |  2 +-
 board/sifive/unmatched/unmatched.env |  2 +-
 5 files changed, 21 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/lib/bdinfo.c

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-05-30  8:56 Leo Liang
  2024-06-03 17:42 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-05-30  8:56 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit 46ff00bea5dd2dd247d5e2fdadbf5dcf8653cd9a:

  Merge tag 'tpm-master-27052024' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2024-05-27 08:56:02 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 1d29c718b7ba09807f8060796d9c21772e3c1b52:

  andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND (2024-05-30 16:01:13 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20920
----------------------------------------------------------------

- board: fix support for icicle
- board: support Star64 board
- andes: minor fixes
- riscv: deprecate cache enablement in start.S

----------------------------------------------------------------
Conor Dooley (2):
      board: microchip: icicle: correct type for node offset
      board: microchip: icicle: make both ethernets optional

H Bell (2):
      board: starfive: support Pine64 Star64 board
      board: starfive: support Pine64 Star64 board

Leo Yu-Chi Liang (3):
      andes: l2 cache driver: fixes typos and cctl status
      riscv: remove cache enablement in start.S
      andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND

 arch/riscv/cpu/andes/cache.c                      |   4 +-
 arch/riscv/cpu/start.S                            |   4 -
 arch/riscv/include/asm/arch-andes/csr.h           |   2 +-
 board/microchip/mpfs_icicle/mpfs_icicle.c         |  25 +--
 board/starfive/visionfive2/spl.c                  |  89 ++++++++++
 board/starfive/visionfive2/starfive_visionfive2.c |   4 +
 doc/board/starfive/index.rst                      |   1 +
 doc/board/starfive/pine64_star64.rst              | 201 ++++++++++++++++++++++
 drivers/cache/cache-andes-l2.c                    |   8 +-
 9 files changed, 310 insertions(+), 28 deletions(-)
 create mode 100644 doc/board/starfive/pine64_star64.rst

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-05-14 13:28 Leo Liang
  2024-05-14 16:14 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-05-14 13:28 UTC (permalink / raw)
  To: trini; +Cc: u-boot, ycliang, rick

Hi Tom,

The following changes since commit c8ffd1356d42223cbb8c86280a083cc3c93e6426:

  Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" (2024-05-13 09:15:51 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa:

  andes: Unify naming policy for Andes related source (2024-05-14 18:50:47 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20690
----------------------------------------------------------------

- RISC-V: Add NULL check after parsing compatible string
- Board: Add Milk-V Mars CM board
- Andes: Unify naming policy 

----------------------------------------------------------------
Hanyuan Zhao (1):
      riscv: add NULL check before calling strlen in the riscv cpu's get_desc()

Heinrich Schuchardt (6):
      board: starfive: function to read eMMC size
      board: add support for Milk-V Mars CM
      doc: Milk-V Mars CM and Milk-V Mars CM Lite
      configs: visionfive2: enable SPL_YMODEM_SUPPORT
      starfive: add mac vendor sub-command
      riscv: simplify backtrace report

Leo Yu-Chi Liang (1):
      andes: Unify naming policy for Andes related source

 arch/riscv/Kconfig                                 |   4 +-
 arch/riscv/cpu/{andesv5 => andes}/Kconfig          |   4 +-
 arch/riscv/cpu/{andesv5 => andes}/Makefile         |   0
 arch/riscv/cpu/{andesv5 => andes}/cache.c          |  12 +-
 arch/riscv/cpu/{andesv5 => andes}/cpu.c            |   0
 arch/riscv/cpu/{andesv5 => andes}/spl.c            |   0
 arch/riscv/include/asm/arch-jh7110/eeprom.h        |   7 +
 arch/riscv/lib/interrupts.c                        |  16 +-
 board/{AndesTech => andestech}/ae350/Kconfig       |   6 +-
 board/{AndesTech => andestech}/ae350/MAINTAINERS   |   2 +-
 board/{AndesTech => andestech}/ae350/Makefile      |   0
 board/{AndesTech => andestech}/ae350/ae350.c       |   2 +-
 board/starfive/visionfive2/Kconfig                 |   9 +
 board/starfive/visionfive2/spl.c                   |  28 ++-
 board/starfive/visionfive2/starfive_visionfive2.c  |  11 +-
 .../starfive/visionfive2/visionfive2-i2c-eeprom.c  |  43 ++++-
 configs/starfive_visionfive2_defconfig             |   1 +
 doc/board/{AndesTech => andestech}/adp-ag101p.rst  |   0
 doc/board/{AndesTech => andestech}/ae350.rst       |   0
 doc/board/{AndesTech => andestech}/index.rst       |   0
 doc/board/index.rst                                |   2 +-
 doc/board/starfive/index.rst                       |   3 +-
 doc/board/starfive/milk-v_mars_cm.rst              | 193 +++++++++++++++++++++
 drivers/cache/Kconfig                              |   6 +-
 drivers/cache/Makefile                             |   2 +-
 drivers/cache/{cache-v5l2.c => cache-andes-l2.c}   |  40 ++---
 drivers/cpu/riscv_cpu.c                            |   2 +-
 27 files changed, 337 insertions(+), 56 deletions(-)
 rename arch/riscv/cpu/{andesv5 => andes}/Kconfig (91%)
 rename arch/riscv/cpu/{andesv5 => andes}/Makefile (100%)
 rename arch/riscv/cpu/{andesv5 => andes}/cache.c (90%)
 rename arch/riscv/cpu/{andesv5 => andes}/cpu.c (100%)
 rename arch/riscv/cpu/{andesv5 => andes}/spl.c (100%)
 rename board/{AndesTech => andestech}/ae350/Kconfig (91%)
 rename board/{AndesTech => andestech}/ae350/MAINTAINERS (95%)
 rename board/{AndesTech => andestech}/ae350/Makefile (100%)
 rename board/{AndesTech => andestech}/ae350/ae350.c (99%)
 rename doc/board/{AndesTech => andestech}/adp-ag101p.rst (100%)
 rename doc/board/{AndesTech => andestech}/ae350.rst (100%)
 rename doc/board/{AndesTech => andestech}/index.rst (100%)
 create mode 100644 doc/board/starfive/milk-v_mars_cm.rst
 rename drivers/cache/{cache-v5l2.c => cache-andes-l2.c} (84%)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-05-01 16:38 Leo Liang
  2024-05-02 14:42 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-05-01 16:38 UTC (permalink / raw)
  To: trini; +Cc: ycliang, rick, u-boot

Hi Tom,

The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432:

  Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f:

  board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 00:01:18 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 
----------------------------------------------------------------

- RISC-V: cmd: Add SBI implementation ID and extension ID
- Board: Rename spl_soc_init to spl_dram_init
- Board: milkv_duo: Add SPI NOR flash, Ethernet, Sysreset support

----------------------------------------------------------------
Heinrich Schuchardt (2):
      cmd: sbi: add Supervisor Software Events extension
      cmd: sbi: add coreboot and oreboot implementation IDs

Kongyang Liu (10):
      mmc: cv1800b: Add transmit tap delay config to fix write error
      sysreset: cv1800b: Add sysreset driver for cv1800b SoC
      board: sophgo: milkv_duo: Bind sysreset driver
      configs: milkv_duo: Add sysreset configs
      board: milkv_duo: Add init code for Milk-V Duo ethernet
      riscv: dts: sophgo: Add ethernet node
      configs: milkv_duo: Add ethernet configs
      spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC
      riscv: dts: sophgo: Add spi nor flash controller node
      configs: milkv_duo: Add spi nor configs

Lukas Funke (2):
      board: sifive: Rename spl_soc_init() to spl_dram_init()
      board: starfive: Rename spl_soc_init() to spl_dram_init()

Yu Chien Peter Lin (1):
      riscv: andesv5: Set default cache line size to 64-bytes

 arch/riscv/cpu/andesv5/Kconfig           |   1 +
 arch/riscv/cpu/fu540/spl.c               |   2 +-
 arch/riscv/cpu/fu740/spl.c               |   2 +-
 arch/riscv/cpu/jh7110/spl.c              |   2 +-
 arch/riscv/dts/cv1800b-milkv-duo.dts     |  18 ++
 arch/riscv/dts/cv18xx.dtsi               |  40 ++++
 arch/riscv/include/asm/arch-fu540/spl.h  |   2 +-
 arch/riscv/include/asm/arch-fu740/spl.h  |   2 +-
 arch/riscv/include/asm/arch-jh7110/spl.h |   2 +-
 arch/riscv/include/asm/sbi.h             |   1 +
 board/sifive/unleashed/spl.c             |   4 +-
 board/sifive/unmatched/spl.c             |   4 +-
 board/sophgo/milkv_duo/Makefile          |   3 +-
 board/sophgo/milkv_duo/board.c           |  10 +
 board/sophgo/milkv_duo/ethernet.c        |  79 ++++++++
 board/sophgo/milkv_duo/ethernet.h        |  11 ++
 board/starfive/visionfive2/spl.c         |   4 +-
 cmd/riscv/sbi.c                          |   3 +
 configs/milkv_duo_defconfig              |  10 +
 drivers/mmc/cv1800b_sdhci.c              |   4 +-
 drivers/net/designware.c                 |   1 +
 drivers/spi/Kconfig                      |   8 +
 drivers/spi/Makefile                     |   1 +
 drivers/spi/cv1800b_spif.c               | 321 +++++++++++++++++++++++++++++++
 drivers/sysreset/Kconfig                 |   5 +
 drivers/sysreset/Makefile                |   1 +
 drivers/sysreset/sysreset_cv1800b.c      |  64 ++++++
 27 files changed, 591 insertions(+), 14 deletions(-)
 create mode 100644 board/sophgo/milkv_duo/ethernet.c
 create mode 100644 board/sophgo/milkv_duo/ethernet.h
 create mode 100644 drivers/spi/cv1800b_spif.c
 create mode 100644 drivers/sysreset/sysreset_cv1800b.c
 
 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-04-09  8:25 Leo Liang
  2024-04-10  0:43 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-04-09  8:25 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 069d07396e30aa9be396c1dd3fc158ac199e6843:

  Merge tag 'efi-2024-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-04-08 14:33:59 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to c1f78a4f632276bb4d77f8c79fe203709a9fa397:

  doc: describe Milk-V Mars board (2024-04-09 11:30:37 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20256
----------------------------------------------------------------

- RISC-V: Support backtrace and improve isa extension parsing
- cpu: Add cv1800b SoC support
- board: Add Milk-V Mars board support
- board: Add Milk-V Duo SD card support

----------------------------------------------------------------
Ben Dooks (1):
      riscv: add backtrace support

Conor Dooley (2):
      riscv: don't read riscv, isa in the riscv cpu's get_desc()
      riscv: support extension probing using riscv, isa-extensions

Heinrich Schuchardt (7):
      riscv: starfive: MMC card detect
      riscv: do not set default fdt for VisionFive 2
      eeprom: starfive: function get_product_id_from_eeprom()
      riscv: set fdtfile on Milk-V Mars
      board: starfive: support Milk-V Mars board
      riscv: starfive: avoid including common.h
      doc: describe Milk-V Mars board

Kongyang Liu (5):
      riscv: cpu: cv1800b: Add support for cv1800b SoC
      riscv: cache: Implement dcache for cv1800b
      mmc: cv1800b: Add sdhci driver support for cv1800b SoC
      riscv: dts: sophgo: Add clk node and sdhci node
      configs: milkv_duo: Add SD card configs

Łukasz Stelmach (1):
      riscv: Move virtio scan to board_late_init()

 arch/riscv/Kconfig                                 |  22 ++++
 arch/riscv/Makefile                                |   4 +
 arch/riscv/cpu/cpu.c                               |  60 +++++++----
 arch/riscv/cpu/cv1800b/Kconfig                     |  12 +++
 arch/riscv/cpu/cv1800b/Makefile                    |   7 ++
 arch/riscv/cpu/cv1800b/cache.c                     |  45 ++++++++
 arch/riscv/cpu/cv1800b/cpu.c                       |   9 ++
 arch/riscv/cpu/cv1800b/dram.c                      |  21 ++++
 arch/riscv/cpu/start.S                             |   1 +
 arch/riscv/dts/cv1800b-milkv-duo.dts               |   8 ++
 arch/riscv/dts/cv1800b.dtsi                        |   4 +
 arch/riscv/dts/cv18xx.dtsi                         |  22 ++++
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi   |   2 +-
 arch/riscv/include/asm/arch-jh7110/eeprom.h        |   9 ++
 arch/riscv/lib/interrupts.c                        |  35 +++++++
 board/emulation/qemu-riscv/qemu-riscv.c            |  12 +--
 board/sophgo/milkv_duo/Kconfig                     |   4 +-
 board/starfive/visionfive2/spl.c                   | 100 +++++++++++++++---
 board/starfive/visionfive2/starfive_visionfive2.c  |  48 ++++++---
 .../starfive/visionfive2/visionfive2-i2c-eeprom.c  |   9 +-
 configs/milkv_duo_defconfig                        |  10 ++
 configs/starfive_visionfive2_defconfig             |   1 -
 doc/board/starfive/index.rst                       |   1 +
 doc/board/starfive/milk-v_mars.rst                 | 111 ++++++++++++++++++++
 doc/board/starfive/visionfive2.rst                 |  18 ++++
 drivers/cpu/riscv_cpu.c                            |   8 +-
 drivers/mmc/Kconfig                                |  13 +++
 drivers/mmc/Makefile                               |   1 +
 drivers/mmc/cv1800b_sdhci.c                        | 116 +++++++++++++++++++++
 29 files changed, 649 insertions(+), 64 deletions(-)
 create mode 100644 arch/riscv/cpu/cv1800b/Kconfig
 create mode 100644 arch/riscv/cpu/cv1800b/Makefile
 create mode 100644 arch/riscv/cpu/cv1800b/cache.c
 create mode 100644 arch/riscv/cpu/cv1800b/cpu.c
 create mode 100644 arch/riscv/cpu/cv1800b/dram.c
 create mode 100644 doc/board/starfive/milk-v_mars.rst
 create mode 100644 drivers/mmc/cv1800b_sdhci.c

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-03-26 13:22 Leo Liang
  2024-03-27 12:12 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-03-26 13:22 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc:

  Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded3175ac5de3ed2b784:

  spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR (2024-03-26 17:31:24 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20075
----------------------------------------------------------------

- Fix RISC-V falcon mode booting issue

----------------------------------------------------------------
Randolph (1):
      spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR

 common/spl/spl_opensbi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-03-12  8:51 Leo Liang
  2024-03-12 18:52 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-03-12  8:51 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d:

  Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 544af8207c69829b1697f3aa5dd682a299a6dea4:

  board: starfive: maintainer: Add visionfive2 PCIe driver (2024-03-12 14:36:13 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19910
----------------------------------------------------------------

* riscv: lib: improve extension detection
* riscv: sbi: fix display format and global variable storage
* sifive: fu740: reduce DDR speed
* board: starfive vf2: switch to standard boot and fix DTS

----------------------------------------------------------------
Bo Gan (1):
      riscv: dts: jh7110: Enable PLL node in SPL

Conor Dooley (1):
      riscv: cpu: improve multi-letter extension detection in supports_extension()

Heinrich Schuchardt (3):
      serial: move sbi_dbcn_available to .data section
      cmd: sbi: Correctly display unknown implementation IDs
      cmd: sbi: formatting PolarFire Hart Software Services version

Leon M. Busch-George (1):
      riscv: dts: jh7110: fix indentation

Minda Chen (2):
      board: starfive: Update maintainer of VisionFive v2 board
      board: starfive: maintainer: Add visionfive2 PCIe driver

Nam Cao (1):
      starfive: visionfive2: switch to standard boot

Thomas Perrot (1):
      riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s

 arch/riscv/cpu/cpu.c                               | 22 ++++++++++++++++------
 arch/riscv/dts/fu740-c000-u-boot.dtsi              |  2 +-
 .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi   |  2 +-
 arch/riscv/dts/jh7110-u-boot.dtsi                  |  4 ++++
 board/starfive/visionfive2/MAINTAINERS             |  3 ++-
 cmd/riscv/sbi.c                                    |  3 ++-
 configs/starfive_visionfive2_defconfig             |  2 +-
 drivers/serial/serial_sbi.c                        |  2 +-
 include/configs/starfive-visionfive2.h             | 14 +-------------
 9 files changed, 29 insertions(+), 25 deletions(-)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2024-01-31 10:21 Leo Liang
  2024-01-31 14:14 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2024-01-31 10:21 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick

Hi Tom,

The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919:

  Merge tag 'clk-2024.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 6882255ac3107c58e1153311df8a8270087f8cb3:

  riscv: dts: starfive: add regulator device (2024-01-31 16:52:53 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19505
----------------------------------------------------------------

* Add RISC-V falcon mode documentation
* Add Clang build support
* Add cmd to detect Debug Trigger Extension support

* Add PWM setting for Unmatched board
* Add Milk-V Duo board support
* Add new device node and enable new config option for VisionFive2 board
* Add second virtio device for RISC-V QEMU

----------------------------------------------------------------
Aurelien Jarno (3):
      board: starfive: handle compatible property in dynamic DT configuration
      riscv: qemu: enable booting on a second virtio device
      configs: visionfive2: Disable ENV_IS_NOWHERE

Heinrich Schuchardt (1):
      cmd: sbi: add support for Debug Trigger Extension

Kongyang Liu (3):
      riscv: dts: sophgo: add basic device tree for Milk-V Duo board
      riscv: sophgo: milkv_duo: initial support added
      doc: sophgo: milkv_duo: document Milk-V Duo board

Lukasz Tekieli (2):
      net: phy: motorcomm: configure pad drive strength register
      board: visionfive2: configure PHY pad drive strength

Nam Cao (2):
      riscv: dts: jh7110: add power management unit controller node
      riscv: dts: starfive: add regulator device

Randolph (3):
      doc: falcon: riscv: Falcon Mode boot on RISC-V
      spl: riscv: falcon: move fdt blob to specified address
      configs: andes: add the fdt blob copy address for SPL

Vincent Chen (1):
      board: sifive: spl: Initialized the PWM setting in the SPL stage

kleines Filmröllchen (1):
      riscv: Support building with Clang

 arch/riscv/Kconfig                               |   4 +
 arch/riscv/config.mk                             |   2 +-
 arch/riscv/dts/Makefile                          |   1 +
 arch/riscv/dts/cv1800b-milkv-duo.dts             |  38 +++++
 arch/riscv/dts/cv1800b.dtsi                      |  18 +++
 arch/riscv/dts/cv18xx.dtsi                       | 192 +++++++++++++++++++++++
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi |   5 +
 arch/riscv/dts/jh7110.dtsi                       |   6 +
 arch/riscv/include/asm/arch-fu740/eeprom.h       |  15 ++
 arch/riscv/include/asm/sbi.h                     |   1 +
 board/AndesTech/ae350/ae350.c                    |  25 ---
 board/sifive/unmatched/spl.c                     |  52 ++++++
 board/sophgo/milkv_duo/Kconfig                   |  28 ++++
 board/sophgo/milkv_duo/MAINTAINERS               |   6 +
 board/sophgo/milkv_duo/Makefile                  |   5 +
 board/sophgo/milkv_duo/board.c                   |   9 ++
 board/starfive/visionfive2/spl.c                 |  12 ++
 cmd/riscv/sbi.c                                  |   1 +
 common/spl/Kconfig                               |   2 +-
 common/spl/spl_opensbi.c                         |  15 ++
 configs/ae350_rv32_falcon_defconfig              |   1 +
 configs/ae350_rv32_falcon_xip_defconfig          |   1 +
 configs/ae350_rv64_falcon_defconfig              |   1 +
 configs/ae350_rv64_falcon_xip_defconfig          |   1 +
 configs/milkv_duo_defconfig                      |  23 +++
 configs/starfive_visionfive2_defconfig           |   1 -
 doc/board/index.rst                              |   1 +
 doc/board/sophgo/index.rst                       |   8 +
 doc/board/sophgo/milkv_duo.rst                   |  64 ++++++++
 doc/develop/falcon.rst                           | 158 +++++++++++++++++++
 drivers/net/phy/motorcomm.c                      | 130 +++++++++++++++
 include/configs/milkv_duo.h                      |  12 ++
 include/configs/qemu-riscv.h                     |   1 +
 33 files changed, 811 insertions(+), 28 deletions(-)
 create mode 100644 arch/riscv/dts/cv1800b-milkv-duo.dts
 create mode 100644 arch/riscv/dts/cv1800b.dtsi
 create mode 100644 arch/riscv/dts/cv18xx.dtsi
 create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h
 create mode 100644 board/sophgo/milkv_duo/Kconfig
 create mode 100644 board/sophgo/milkv_duo/MAINTAINERS
 create mode 100644 board/sophgo/milkv_duo/Makefile
 create mode 100644 board/sophgo/milkv_duo/board.c
 create mode 100644 configs/milkv_duo_defconfig
 create mode 100644 doc/board/sophgo/index.rst
 create mode 100644 doc/board/sophgo/milkv_duo.rst
 create mode 100644 include/configs/milkv_duo.h

 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2023-12-14  2:38 Leo Yu-Chi Liang(梁育齊)
  2023-12-14 12:19 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Yu-Chi Liang(梁育齊) @ 2023-12-14  2:38 UTC (permalink / raw)
  To: trini@konsulko.com
  Cc: u-boot@lists.denx.de,
	Rick Jian-Zhi Chen(陳建志),
	Leo Yu-Chi Liang(梁育齊)

Hi Tom,

The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151:

  Merge tag 'u-boot-imx-20231212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35:

  riscv: sifive: unmatched: migrate to text environment (2023-12-13 16:19:43 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889
----------------------------------------------------------------
- VisionFive2: Enable CONFIG_SYSRESET
- StarFive: Modify starfive timer driver
- AMD/Xilinx: Add MicroBlaze V support
- Unmatched: Migrate to text environment
----------------------------------------------------------------
Jaehoon Chung (2):
      riscv: dts: jh7110: Add a gpio-restart node
      configs: visionfive2: Enable CONFIG_SYSRESET config

Kuan Lim Lee (1):
      timer: starfive: Add Starfive timer support

Michal Simek (1):
      riscv: Add support for AMD/Xilinx MicroBlaze V

Yong-Xuan Wang (1):
      riscv: sifive: unmatched: migrate to text environment

 arch/riscv/Kconfig                               |   4 +
 arch/riscv/dts/Makefile                          |   2 +
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi |   5 ++
 arch/riscv/dts/xilinx-mbv32.dts                  | 106 +++++++++++++++++++++++
 board/sifive/unmatched/unmatched.env             |  19 ++++
 board/xilinx/Kconfig                             |   3 +-
 board/xilinx/common/board.c                      |   5 ++
 board/xilinx/mbv/Kconfig                         |  28 ++++++
 board/xilinx/mbv/MAINTAINERS                     |   7 ++
 board/xilinx/mbv/Makefile                        |   5 ++
 board/xilinx/mbv/board.c                         |  11 +++
 configs/sifive_unmatched_defconfig               |   2 +-
 configs/starfive_visionfive2_defconfig           |   1 +
 configs/xilinx_mbv32_defconfig                   |  30 +++++++
 configs/xilinx_mbv32_smode_defconfig             |  32 +++++++
 drivers/timer/starfive-timer.c                   |  16 ++--
 include/configs/sifive-unmatched.h               |  37 --------
 include/configs/xilinx_mbv.h                     |   6 ++
 18 files changed, 273 insertions(+), 46 deletions(-)
 create mode 100644 arch/riscv/dts/xilinx-mbv32.dts
 create mode 100644 board/sifive/unmatched/unmatched.env
 create mode 100644 board/xilinx/mbv/Kconfig
 create mode 100644 board/xilinx/mbv/MAINTAINERS
 create mode 100644 board/xilinx/mbv/Makefile
 create mode 100644 board/xilinx/mbv/board.c
 create mode 100644 configs/xilinx_mbv32_defconfig
 create mode 100644 configs/xilinx_mbv32_smode_defconfig
 create mode 100644 include/configs/xilinx_mbv.h

Best regards,
Leo


^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2023-12-07 13:46 Leo Liang
  2023-12-09 20:59 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2023-12-07 13:46 UTC (permalink / raw)
  To: trini; +Cc: u-boot, rick, ycliang

Hi Tom,

The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63:

  Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 94533cd9c15a60b74420e53a725fab54d38dd555:

  starfive: visionfive2: add device tree overlay support (2023-12-06 16:05:39 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18812

----------------------------------------------------------------
- StarFive: Add StarFive watchdog driver
- VisionFive2: Support device tree overlay for VisionFive2 board
- Andes: Fix PLIC-SW setting
- RISC-V: Fix NVMe support by implying NVME_PCI for QEMU
- RISC-V: Fix binman for 64 bit format load address
----------------------------------------------------------------
Chanho Park (4):
      clk: starfive: jh7110: Add watchdog clocks
      watchdog: Add StarFive Watchdog driver
      riscv: dts: jh7110: Add watchdog device tree node
      configs: visionfive2: Enable watchdog driver

Heinrich Schuchardt (1):
      risc-v: qemu: imply NVME_PCI

John Clark (1):
      starfive: visionfive2: add device tree overlay support

Randolph (1):
      riscv: binman: fix the load field format

Yu Chien Peter Lin (1):
      riscv: andes: Fix enable register settings of PLICSW

 arch/riscv/dts/binman.dtsi             |  14 +-
 arch/riscv/dts/jh7110.dtsi             |  10 +
 arch/riscv/lib/andes_plicsw.c          |  33 ++--
 board/emulation/qemu-riscv/Kconfig     |   2 +-
 configs/starfive_visionfive2_defconfig |   5 +
 drivers/clk/starfive/clk-jh7110.c      |   9 +
 drivers/watchdog/Kconfig               |   7 +
 drivers/watchdog/Makefile              |   1 +
 drivers/watchdog/starfive_wdt.c        | 329 +++++++++++++++++++++++++++++++++
 include/configs/starfive-visionfive2.h |   1 +
 10 files changed, 382 insertions(+), 29 deletions(-)
 create mode 100644 drivers/watchdog/starfive_wdt.c

 Best regards,
 Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
* [GIT PULL] u-boot-riscv/master
@ 2021-02-26  1:53 Leo Liang
  2021-02-26 17:40 ` Tom Rini
  0 siblings, 1 reply; 76+ messages in thread
From: Leo Liang @ 2021-02-26  1:53 UTC (permalink / raw)
  To: u-boot

Hi Tom,

Please pull some RISC-V updates.
CI result: https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/6505

The following changes since commit cbe607b920bc0827d8fe379ed4f5ae4e2058513e:

  Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze (2021-02-23 10:45:55 -0500)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 5540294fa48598bf1aa8aa4d9084506a19bbd64c:

  riscv: k210: Enable QSPI for spi3 (2021-02-25 18:06:08 +0800)

----------------------------------------------------------------
Heinrich Schuchardt (1):
      cmd/riscv/sbi: support System Reset Extension

Sean Anderson (1):
      riscv: k210: Enable QSPI for spi3

 arch/riscv/dts/k210-maix-bit.dts | 2 ++
 cmd/riscv/sbi.c                  | 1 +
 2 files changed, 3 insertions(+)

Best regards,
Leo

^ permalink raw reply	[flat|nested] 76+ messages in thread
end of thread, other threads:[~2025-10-16 17:38 UTC | newest]

Thread overview: 76+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-02 10:49 [GIT PULL] u-boot-riscv/master Leo Liang
2023-11-02 14:53 ` Tom Rini
  -- strict thread matches above, loose matches on Subject: below --
2025-10-16 12:07 [GIT,PULL] u-boot-riscv/master Leo Liang
2025-10-16 17:38 ` Tom Rini
2025-08-12  8:04 [GIT PULL] u-boot-riscv/master Leo Liang
2025-08-12 15:22 ` Tom Rini
2025-08-13  6:57   ` Leo Liang
2025-08-13 11:16     ` Martin Herren
2025-08-13 11:59       ` Leo Liang
2025-05-21  9:50 Leo Liang
2025-05-21 18:39 ` Tom Rini
2025-05-22 11:28   ` Conor Dooley
2025-05-22 14:45     ` Tom Rini
2025-05-22 15:36       ` Leo Liang
2025-05-22 15:54         ` Tom Rini
2025-05-22 16:40     ` Yao Zi
2025-05-23  9:18       ` Conor Dooley
2025-05-26  3:32       ` Mayuresh Chitale
2025-05-26  9:17         ` Conor Dooley
2025-05-26 14:56           ` Tom Rini
2025-05-26 17:34             ` Mayuresh Chitale
2025-05-26 18:16               ` Tom Rini
2025-05-27 17:10                 ` Mayuresh Chitale
2025-05-27 17:34                   ` Tom Rini
2025-04-25 10:07 Leo Liang
2025-04-25 10:35 ` Yao Zi
2025-04-26 14:14   ` Tom Rini
2025-04-25 12:57 ` E Shattow
2025-04-25 13:02   ` E Shattow
2025-04-25 23:43 ` Tom Rini
2025-04-26  1:13   ` E Shattow
2025-04-26 14:14     ` Tom Rini
2025-04-27  7:47       ` E Shattow
2025-03-25  6:19 Leo Liang
2025-03-25 20:18 ` Tom Rini
2025-03-06 12:18 Leo Liang
2025-03-07 11:20 ` Yao Zi
2025-02-20  5:13 Leo Liang
2025-02-20 17:19 ` Tom Rini
2025-02-03  8:17 Leo Liang
2025-02-03 21:26 ` Tom Rini
2025-01-17  1:53 Leo Liang
2025-01-17 17:56 ` Tom Rini
2024-11-27 13:08 Leo Liang
2024-11-27 18:54 ` Tom Rini
2024-11-06 12:12 Leo Liang
2024-11-08 16:51 ` Tom Rini
2024-11-11 13:24 ` Tom Rini
2024-10-29 12:33 Leo Liang
2024-10-29 16:37 ` Tom Rini
2024-10-28 12:24 Leo Liang
2024-10-28 19:33 ` Tom Rini
2024-07-22  8:29 Leo Liang
2024-07-22 19:31 ` Tom Rini
2024-05-30  8:56 Leo Liang
2024-06-03 17:42 ` Tom Rini
2024-05-14 13:28 Leo Liang
2024-05-14 16:14 ` Tom Rini
2024-05-01 16:38 Leo Liang
2024-05-02 14:42 ` Tom Rini
2024-04-09  8:25 Leo Liang
2024-04-10  0:43 ` Tom Rini
2024-03-26 13:22 Leo Liang
2024-03-27 12:12 ` Tom Rini
2024-03-12  8:51 Leo Liang
2024-03-12 18:52 ` Tom Rini
2024-01-31 10:21 Leo Liang
2024-01-31 14:14 ` Tom Rini
2023-12-14  2:38 Leo Yu-Chi Liang(梁育齊)
2023-12-14 12:19 ` Tom Rini
2023-12-14 12:46   ` Leo Liang
2023-12-14 14:39     ` Tom Rini
2023-12-07 13:46 Leo Liang
2023-12-09 20:59 ` Tom Rini
2021-02-26  1:53 Leo Liang
2021-02-26 17:40 ` Tom Rini

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox