[GIT PULL] u-boot-riscv/next

[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit fdefb4e194c65777fa11479119adaa71651f41d4:

  Merge tag 'efi-next-20231217' of https://source.denx.de/u-boot/custodians/u-boot-efi into next (2023-12-17 09:11:06 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 44a792c99498f5a9d3526019779d66585978c491:

  riscv: sifive: unmatched: migrate to text environment (2023-12-18 11:09:01 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18996
----------------------------------------------------------------
- VisionFive2: Enable CONFIG_SYSRESET
- StarFive: Modify starfive timer driver
- AMD/Xilinx: Add MicroBlaze V support
- Unmatched: Migrate to text environment
----------------------------------------------------------------
Jaehoon Chung (2):
      riscv: dts: jh7110: Add a gpio-restart node
      configs: visionfive2: Enable CONFIG_SYSRESET config

Kuan Lim Lee (1):
      timer: starfive: Add Starfive timer support

Michal Simek (1):
      riscv: Add support for AMD/Xilinx MicroBlaze V

Yong-Xuan Wang (1):
      riscv: sifive: unmatched: migrate to text environment

 arch/riscv/Kconfig                               |   4 +
 arch/riscv/dts/Makefile                          |   2 +
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi |   5 ++
 arch/riscv/dts/xilinx-mbv32.dts                  | 106 +++++++++++++++++++++++
 board/sifive/unmatched/unmatched.env             |  19 ++++
 board/xilinx/Kconfig                             |   3 +-
 board/xilinx/common/board.c                      |   5 ++
 board/xilinx/mbv/Kconfig                         |  28 ++++++
 board/xilinx/mbv/MAINTAINERS                     |   7 ++
 board/xilinx/mbv/Makefile                        |   5 ++
 board/xilinx/mbv/board.c                         |  11 +++
 configs/sifive_unmatched_defconfig               |   2 +-
 configs/starfive_visionfive2_defconfig           |   1 +
 configs/xilinx_mbv32_defconfig                   |  30 +++++++
 configs/xilinx_mbv32_smode_defconfig             |  32 +++++++
 drivers/timer/starfive-timer.c                   |  16 ++--
 include/configs/sifive-unmatched.h               |  37 --------
 include/configs/xilinx_mbv.h                     |   6 ++
 18 files changed, 273 insertions(+), 46 deletions(-)
 create mode 100644 arch/riscv/dts/xilinx-mbv32.dts
 create mode 100644 board/sifive/unmatched/unmatched.env
 create mode 100644 board/xilinx/mbv/Kconfig
 create mode 100644 board/xilinx/mbv/MAINTAINERS
 create mode 100644 board/xilinx/mbv/Makefile
 create mode 100644 board/xilinx/mbv/board.c
 create mode 100644 configs/xilinx_mbv32_defconfig
 create mode 100644 configs/xilinx_mbv32_smode_defconfig
 create mode 100644 include/configs/xilinx_mbv.h

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

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On Mon, Dec 18, 2023 at 07:44:15PM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit fdefb4e194c65777fa11479119adaa71651f41d4:
> 
>   Merge tag 'efi-next-20231217' of https://source.denx.de/u-boot/custodians/u-boot-efi into next (2023-12-17 09:11:06 -0500)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to 44a792c99498f5a9d3526019779d66585978c491:
> 
>   riscv: sifive: unmatched: migrate to text environment (2023-12-18 11:09:01 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18996

Applied to u-boot/next, thanks!

-- 
Tom

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[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84:

  bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf:

  andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106
----------------------------------------------------------------
- Andes: Enable Andes CPU memboost and ECC feature by default 
- Sifive: Add private L2 cache driver
----------------------------------------------------------------
Leo Yu-Chi Liang (6):
      andes: csr.h: Clean up CSR definition
      andes: ae350: Implement cache switch via Kconfig
      andes: cpu: Enable memboost feature
      andes: cpu: Enable cache and TLB ECC support
      andes: ae350: Save cpu name to env
      andes: ae350: Enable MISC_INIT_R for ae350 platform

Michal Simek (1):
      riscv: Extend board compatible string with "qemu,mbv"

Zong Li (2):
      cache: add sifive private L2 cache driver
      riscv: cache: support cache enable in SPL stage

 arch/riscv/cpu/andesv5/cpu.c            | 33 ++++++++++++++++++-------
 arch/riscv/dts/xilinx-mbv32.dts         |  2 +-
 arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++---------
 arch/riscv/include/asm/csr.h            |  1 +
 arch/riscv/lib/sifive_cache.c           | 21 ++++++++++++++++
 board/AndesTech/ae350/ae350.c           | 26 ++++++++++++++++++-
 configs/ae350_rv32_defconfig            |  5 ++--
 configs/ae350_rv32_spl_defconfig        |  5 ++--
 configs/ae350_rv32_spl_xip_defconfig    |  5 ++--
 configs/ae350_rv32_xip_defconfig        |  5 ++--
 configs/ae350_rv64_defconfig            |  5 ++--
 configs/ae350_rv64_spl_defconfig        |  5 ++--
 configs/ae350_rv64_spl_xip_defconfig    |  5 ++--
 configs/ae350_rv64_xip_defconfig        |  5 ++--
 drivers/cache/Kconfig                   |  7 ++++++
 drivers/cache/Makefile                  |  1 +
 drivers/cache/cache-sifive-pl2.c        | 44 +++++++++++++++++++++++++++++++++
 17 files changed, 165 insertions(+), 39 deletions(-)
 create mode 100644 drivers/cache/cache-sifive-pl2.c

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

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On Thu, Dec 28, 2023 at 01:38:11PM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84:
> 
>   bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf:
> 
>   andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106

Applied to u-boot/next, thanks!

-- 
Tom

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[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 28dc47038edc4e93f32d75a357131bcf01a18d85:

  Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next (2024-10-05 11:19:24 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to f07daa5967f65771f90221ee9bfad9814e549647:

  riscv: mbv: Align DT with QEMU (2024-10-28 17:49:25 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23049

----------------------------------------------------------------
Michal Simek (1):
      riscv: mbv: Align DT with QEMU

 arch/riscv/dts/xilinx-mbv32.dts | 30 ++++++++++--------------------
 board/xilinx/mbv/Kconfig        |  6 +++---
 configs/xilinx_mbv32_defconfig  | 12 ++++++------
 3 files changed, 19 insertions(+), 29 deletions(-)

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

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On Mon, Oct 28, 2024 at 08:25:55PM +0800, Leo Liang wrote:
> Hi Tom,
> 
> The following changes since commit 28dc47038edc4e93f32d75a357131bcf01a18d85:
> 
>   Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next (2024-10-05 11:19:24 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to f07daa5967f65771f90221ee9bfad9814e549647:
> 
>   riscv: mbv: Align DT with QEMU (2024-10-28 17:49:25 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23049
> 
> ----------------------------------------------------------------
> Michal Simek (1):
>       riscv: mbv: Align DT with QEMU
> 
>  arch/riscv/dts/xilinx-mbv32.dts | 30 ++++++++++--------------------
>  board/xilinx/mbv/Kconfig        |  6 +++---
>  configs/xilinx_mbv32_defconfig  | 12 ++++++------
>  3 files changed, 19 insertions(+), 29 deletions(-)

Why is this for -next and not master? We're not so far in to the cycle
that next is open, and this seems clear enough to pull in today. Thanks.

-- 
Tom

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Re: [GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

On Mon, Oct 28, 2024 at 09:20:10AM -0600, Tom Rini wrote:
> [EXTERNAL MAIL]
> Date: Mon, 28 Oct 2024 09:20:10 -0600
> From: Tom Rini <trini@konsulko.com>
> To: Leo Liang <ycliang@andestech.com>
> Cc: u-boot@lists.denx.de, rick@andestech.com
> Subject: Re: [GIT PULL] u-boot-riscv/next
> 
> On Mon, Oct 28, 2024 at 08:25:55PM +0800, Leo Liang wrote:
> > Hi Tom,
> > 
> > The following changes since commit 28dc47038edc4e93f32d75a357131bcf01a18d85:
> > 
> >   Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next (2024-10-05 11:19:24 -0600)
> > 
> > are available in the Git repository at:
> > 
> >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > 
> > for you to fetch changes up to f07daa5967f65771f90221ee9bfad9814e549647:
> > 
> >   riscv: mbv: Align DT with QEMU (2024-10-28 17:49:25 +0800)
> > 
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23049
> > 
> > ----------------------------------------------------------------
> > Michal Simek (1):
> >       riscv: mbv: Align DT with QEMU
> > 
> >  arch/riscv/dts/xilinx-mbv32.dts | 30 ++++++++++--------------------
> >  board/xilinx/mbv/Kconfig        |  6 +++---
> >  configs/xilinx_mbv32_defconfig  | 12 ++++++------
> >  3 files changed, 19 insertions(+), 29 deletions(-)
> 
> Why is this for -next and not master? We're not so far in to the cycle
> that next is open, and this seems clear enough to pull in today. Thanks.
> 
> -- 
> Tom


Michal said that this patch might have to wait for its counterpart in QEMU be merged.
(https://lore.kernel.org/all/20241017072507.4033413-1-sai.pavan.boddu@amd.com/)
But like you said, this seems clear enough for master. I will create another PR for this patch. 
Thanks!

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Michal Simek]

út 29. 10. 2024 v 10:35 odesílatel Leo Liang <ycliang@andestech.com> napsal:
>
> Hi Tom,
>
> On Mon, Oct 28, 2024 at 09:20:10AM -0600, Tom Rini wrote:
> > [EXTERNAL MAIL]
> > Date: Mon, 28 Oct 2024 09:20:10 -0600
> > From: Tom Rini <trini@konsulko.com>
> > To: Leo Liang <ycliang@andestech.com>
> > Cc: u-boot@lists.denx.de, rick@andestech.com
> > Subject: Re: [GIT PULL] u-boot-riscv/next
> >
> > On Mon, Oct 28, 2024 at 08:25:55PM +0800, Leo Liang wrote:
> > > Hi Tom,
> > >
> > > The following changes since commit 28dc47038edc4e93f32d75a357131bcf01a18d85:
> > >
> > >   Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next (2024-10-05 11:19:24 -0600)
> > >
> > > are available in the Git repository at:
> > >
> > >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > >
> > > for you to fetch changes up to f07daa5967f65771f90221ee9bfad9814e549647:
> > >
> > >   riscv: mbv: Align DT with QEMU (2024-10-28 17:49:25 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23049
> > >
> > > ----------------------------------------------------------------
> > > Michal Simek (1):
> > >       riscv: mbv: Align DT with QEMU
> > >
> > >  arch/riscv/dts/xilinx-mbv32.dts | 30 ++++++++++--------------------
> > >  board/xilinx/mbv/Kconfig        |  6 +++---
> > >  configs/xilinx_mbv32_defconfig  | 12 ++++++------
> > >  3 files changed, 19 insertions(+), 29 deletions(-)
> >
> > Why is this for -next and not master? We're not so far in to the cycle
> > that next is open, and this seems clear enough to pull in today. Thanks.
> >
> > --
> > Tom
>
>
> Michal said that this patch might have to wait for its counterpart in QEMU be merged.
> (https://lore.kernel.org/all/20241017072507.4033413-1-sai.pavan.boddu@amd.com/)
> But like you said, this seems clear enough for master. I will create another PR for this patch.

Likely the address map won't change.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 3b3c7280b82b1f08807a070ac066cd02919dfde1:

  smbios: address build warning (2024-12-15 11:41:32 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to e59241f8b1315168b7a8a2645c3d3fe73ea5d6d9:

  riscv: spl: add FIT name for RISC-V Falcon mode (2024-12-18 13:19:16 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23926
----------------------------------------------------------------
- Board: Support LicheeRV Nano
- Board: Support bananapi-f3
- Board: Switch to OF_UPSTREAM for StarFive JH7110
- Board: Add sdhci driver for TH1520 SoC
----------------------------------------------------------------
Hal Feng (12):
      dts: starfive: Switch to using upstream DT
      riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT
      mmc: dw_mmc: Add "starfive, jh7110-mmc" compatible to match upstream DT
      pcie: starfive: Make the driver compatible with upstream DT
      riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi
      riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards
      board: starfive: spl: Drop the unneeded DT modification code
      configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 based board DT
      riscv: dts: jh7110: Support multiple DTBs in a Fit image
      board: starfive: spl: Fix the wrong use of CONFIG_IS_ENABLED()
      board: starfive: spl: Support multiple DTBs for JH7110 based boards
      riscv: cpu: jh7110: Sort the list of imply statements

Kongyang Liu (2):
      riscv: spacemit: bananapi_f3: initial support added
      doc: spacemit: bananapi_f3: document Banana Pi F3 board

Maksim Kiselev (3):
      mmc: snps_sdhci: Add sdhci driver support for TH1520 SoC
      riscv: dts: t-head: Add sdhci and emmc nodes
      configs: th1520_lpi4a: enable mmc controller support

Randolph (1):
      riscv: spl: add FIT name for RISC-V Falcon mode

Thomas Bonnefille (3):
      doc: add LicheeRV Nano and SG2002 SoC
      riscv: dts: sophgo: add device tree for LicheeRV Nano
      board: add support for LicheeRV Nano

 arch/riscv/Kconfig                                 |   9 +
 arch/riscv/cpu/jh7110/Kconfig                      |  19 +-
 arch/riscv/cpu/k1/Kconfig                          |  18 +
 arch/riscv/cpu/k1/Makefile                         |   6 +
 arch/riscv/cpu/k1/cpu.c                            |   9 +
 arch/riscv/cpu/k1/dram.c                           |  54 ++
 arch/riscv/dts/Makefile                            |   4 +-
 arch/riscv/dts/jh7110-common-u-boot.dtsi           | 195 ++++++
 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi       |   6 +
 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi    |   6 +
 .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi   | 117 ----
 .../jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi |   6 +
 .../jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi |   6 +
 arch/riscv/dts/jh7110-starfive-visionfive-2.dts    |  11 -
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi   | 380 ----------
 arch/riscv/dts/jh7110-u-boot.dtsi                  |  27 +-
 arch/riscv/dts/jh7110.dtsi                         | 761 ---------------------
 arch/riscv/dts/k1-bananapi-f3.dts                  |  25 +
 arch/riscv/dts/k1.dtsi                             | 459 +++++++++++++
 arch/riscv/dts/sg2002-licheerv-nano-b.dts          |  45 ++
 arch/riscv/dts/sg2002.dtsi                         |  34 +
 arch/riscv/dts/th1520-lichee-module-4a.dtsi        |  18 +
 arch/riscv/dts/th1520.dtsi                         |  34 +
 board/sophgo/licheerv_nano/Kconfig                 |  28 +
 board/sophgo/licheerv_nano/MAINTAINERS             |   5 +
 board/sophgo/licheerv_nano/Makefile                |   5 +
 board/sophgo/licheerv_nano/board.c                 |   9 +
 board/spacemit/bananapi-f3/Kconfig                 |  25 +
 board/spacemit/bananapi-f3/MAINTAINERS             |   6 +
 board/spacemit/bananapi-f3/Makefile                |   5 +
 board/spacemit/bananapi-f3/board.c                 |   9 +
 board/starfive/visionfive2/spl.c                   | 391 +----------
 common/spl/Kconfig                                 |   1 +
 configs/bananapi-f3_defconfig                      |  20 +
 configs/sipeed_licheerv_nano_defconfig             |  47 ++
 configs/starfive_visionfive2_defconfig             |   4 +-
 configs/th1520_lpi4a_defconfig                     |  11 +-
 doc/board/index.rst                                |   1 +
 doc/board/sophgo/index.rst                         |   1 +
 doc/board/sophgo/licheerv_nano.rst                 |  72 ++
 doc/board/spacemit/bananapi-f3.rst                 | 106 +++
 doc/board/spacemit/index.rst                       |   9 +
 drivers/clk/starfive/clk-jh7110-pll.c              |   6 +-
 drivers/clk/starfive/clk-jh7110.c                  |  44 +-
 drivers/mmc/Kconfig                                |  12 +
 drivers/mmc/Makefile                               |   1 +
 drivers/mmc/snps_dw_mmc.c                          |   1 +
 drivers/mmc/snps_sdhci.c                           | 444 ++++++++++++
 drivers/pci/pcie_starfive_jh7110.c                 |  59 +-
 include/configs/bananapi-f3.h                      |  13 +
 include/configs/licheerv_nano.h                    |  24 +
 include/dt-bindings/clock/starfive,jh7110-crg.h    | 258 -------
 include/dt-bindings/reset/starfive,jh7110-crg.h    | 183 -----
 53 files changed, 1909 insertions(+), 2140 deletions(-)
 create mode 100644 arch/riscv/cpu/k1/Kconfig
 create mode 100644 arch/riscv/cpu/k1/Makefile
 create mode 100644 arch/riscv/cpu/k1/cpu.c
 create mode 100644 arch/riscv/cpu/k1/dram.c
 create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
 create mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
 create mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
 create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
 create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
 delete mode 100644 arch/riscv/dts/jh7110.dtsi
 create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts
 create mode 100644 arch/riscv/dts/k1.dtsi
 create mode 100644 arch/riscv/dts/sg2002-licheerv-nano-b.dts
 create mode 100644 arch/riscv/dts/sg2002.dtsi
 create mode 100644 board/sophgo/licheerv_nano/Kconfig
 create mode 100644 board/sophgo/licheerv_nano/MAINTAINERS
 create mode 100644 board/sophgo/licheerv_nano/Makefile
 create mode 100644 board/sophgo/licheerv_nano/board.c
 create mode 100644 board/spacemit/bananapi-f3/Kconfig
 create mode 100644 board/spacemit/bananapi-f3/MAINTAINERS
 create mode 100644 board/spacemit/bananapi-f3/Makefile
 create mode 100644 board/spacemit/bananapi-f3/board.c
 create mode 100644 configs/bananapi-f3_defconfig
 create mode 100644 configs/sipeed_licheerv_nano_defconfig
 create mode 100644 doc/board/sophgo/licheerv_nano.rst
 create mode 100644 doc/board/spacemit/bananapi-f3.rst
 create mode 100644 doc/board/spacemit/index.rst
 create mode 100644 drivers/mmc/snps_sdhci.c
 create mode 100644 include/configs/bananapi-f3.h
 create mode 100644 include/configs/licheerv_nano.h
 delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
 delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

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On Wed, Dec 18, 2024 at 03:49:44PM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit 3b3c7280b82b1f08807a070ac066cd02919dfde1:
> 
>   smbios: address build warning (2024-12-15 11:41:32 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to e59241f8b1315168b7a8a2645c3d3fe73ea5d6d9:
> 
>   riscv: spl: add FIT name for RISC-V Falcon mode (2024-12-18 13:19:16 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23926

Applied to u-boot/next, thanks!

-- 
Tom

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[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit d574229880378081691dc06c430424015be0740c:

  Merge tag 'qcom-next-20250324' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next (2025-03-24 12:38:48 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 9c40d92305db53f71ae31431b99f73ced11f334e:

  Add reset config options for k1 (2025-03-25 16:34:50 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/25323
----------------------------------------------------------------
- board: k1: Add reset driver
- board: starfive: Simplify binman config
- Some modifications on DTS and configs
----------------------------------------------------------------
Heinrich Schuchardt (6):
      configs: SiFive Unmatched: add 'nvme scan' to preboot
      riscv: qemu: imply CONFIG_RNG_RISCV_ZKR
      riscv: dts: add OF_LIST handling to binman.dtsi
      riscv: dts: no default configuration for MULTI_DTB_FIT
      board: starfive: spl: strip off 'starfive/' prefix
      riscv: dts: starfive: remove duplicate itb entries

Huan Zhou (4):
      riscv: dt-binding: k1: Add reset driver binding definition
      riscv: reset: k1: Add reset driver
      riscv: dts: k1: add reset controller node in device tree
      Add reset config options for k1

Jimmy Ho (1):
      RISCV: config: Remove CFG_SYS_SDRAM_BASE

Junhui Liu (1):
      riscv: dts: spacemit: Update UART compatible for k1

Yao Zi (1):
      riscv: dts: cv18xx: Drop unused dummy clocks

 arch/riscv/cpu/k1/Kconfig                       |   1 +
 arch/riscv/dts/binman.dtsi                      |  10 +-
 arch/riscv/dts/cv18xx.dtsi                      |  14 -
 arch/riscv/dts/k1.dtsi                          |  35 +-
 arch/riscv/dts/starfive-visionfive2-binman.dtsi |  76 ----
 board/emulation/qemu-riscv/Kconfig              |   1 +
 board/starfive/visionfive2/spl.c                |   4 +
 configs/bananapi-f3_defconfig                   |   1 +
 configs/sifive_unmatched_defconfig              |   2 +-
 drivers/reset/Kconfig                           |   6 +
 drivers/reset/Makefile                          |   1 +
 drivers/reset/reset-spacemit-k1.c               | 548 ++++++++++++++++++++++++
 include/configs/sifive-unleashed.h              |   1 -
 include/configs/sifive-unmatched.h              |   1 -
 include/dt-bindings/reset/spacemit-k1-reset.h   | 118 +++++
 15 files changed, 713 insertions(+), 106 deletions(-)
 create mode 100644 drivers/reset/reset-spacemit-k1.c
 create mode 100644 include/dt-bindings/reset/spacemit-k1-reset.h

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

On Tue, 25 Mar 2025 18:55:35 +0800, Leo Liang wrote:

> The following changes since commit d574229880378081691dc06c430424015be0740c:
> 
>   Merge tag 'qcom-next-20250324' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next (2025-03-24 12:38:48 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> [...]

Merged into u-boot/next, thanks!

-- 
Tom

[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit c405bab7661dd60420e97a4edeb3162e9d7e02c5:

  Merge tag 'mmc-next-2025-07-02' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next (2025-07-02 07:51:57 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to f62062a64daeb3f3b148372d0afae3821aff16de:

  cache: Update dependency for ANDES_L2_CACHE (2025-07-03 18:11:06 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26936
----------------------------------------------------------------
- RISC-V: Add big-endian build support
- Board: aclint_ipi: Support T-Head C900 CLINT
- Board: mpfs_icicle: Implement board_fdt_blob_setup()/board_fit_config_name_match()
- Driver: pinctrl: Port pin controller driver for T-Head TH1520 SoC
- Driver: cache: Update dependency for ANDES_L2_CACHE
----------------------------------------------------------------
Ben Dooks (2):
      riscv: add build support for big-endian
      riscv: byteorder: add test for big-endian

Conor Dooley (1):
      board: mpfs_icicle: implement board_fdt_blob_setup()/board_fit_config_name_match()

Tom Rini (1):
      cache: Update dependency for ANDES_L2_CACHE

Yao Zi (8):
      riscv: aclint_ipi: Support T-Head C900 CLINT
      riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
      riscv: cpu: th1520: Add a routine to bring up secondary cores
      riscv: dts: th1520: Preserve CLINT node for SPL
      board: thead: licheepi4a: Bring up secondary cores in SPL
      pinctrl: Port pin controller driver for T-Head TH1520 SoC
      riscv: dts: th1520: Add pin controllers
      riscv: cpu: th1520: Enable pinctrl by default

 MAINTAINERS                               |   1 +
 arch/riscv/config.mk                      |  18 +-
 arch/riscv/cpu/th1520/Kconfig             |   1 +
 arch/riscv/cpu/th1520/cpu.c               |  29 +-
 arch/riscv/cpu/th1520/spl.c               |  83 ++++
 arch/riscv/dts/th1520.dtsi                |  29 ++
 arch/riscv/include/asm/arch-th1520/cpu.h  |   1 +
 arch/riscv/include/asm/byteorder.h        |   2 +-
 arch/riscv/lib/aclint_ipi.c               |   5 +
 board/microchip/mpfs_icicle/mpfs_icicle.c |  63 +++
 board/thead/th1520_lpi4a/spl.c            |   3 +
 configs/th1520_lpi4a_defconfig            |   1 +
 drivers/cache/Kconfig                     |   1 +
 drivers/pinctrl/Kconfig                   |   8 +
 drivers/pinctrl/Makefile                  |   1 +
 drivers/pinctrl/pinctrl-th1520.c          | 700 ++++++++++++++++++++++++++++++
 16 files changed, 940 insertions(+), 6 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-th1520.c

Best regards,
Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

On Thu, 03 Jul 2025 22:09:24 +0800, Leo Liang wrote:

> The following changes since commit c405bab7661dd60420e97a4edeb3162e9d7e02c5:
> 
>   Merge tag 'mmc-next-2025-07-02' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next (2025-07-02 07:51:57 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> [...]

Merged into u-boot/next, thanks!

-- 
Tom

[GIT,PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit a209627ed7921f40669f5c0795570d40e77e4cb7:

  Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()" (2025-09-16 16:14:30 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 10fdc2735da3a4825a5172056090eaf41e061627:

  configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig (2025-09-19 19:23:32 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27673
----------------------------------------------------------------
- Switch to upstream devicetree for TH1520 platform
- Remove fdt_high env variable
- Support SMP on RISC-V cores with Zalrsc only
- Make MPFS Generic
- riscv: dts: starfive: prune redundant jh7110-common
----------------------------------------------------------------
E Shattow (4):
      riscv: dts: starfive: prune redundant jh7110-common overrides
      riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next
      riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion
      configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig

Eoin Dickson (1):
      gpio: mpfs_gpio: fix compilation warnings

Greentime Hu (1):
      arch/riscv: Remove unused macro in encoding.h

Hal Feng (1):
      pcie: starfive: Remove the redundant print of probe success

Heinrich Schuchardt (1):
      starfive: avoid NULL dereference in fdt_check_header()

Jamie Gibbons (6):
      board: microchip: icicle: rename all icicle files to generic
      configs/microchip_mpfs_generic_defconfig: add board
      doc: microchip: introduce common sections
      doc: microchip: add mpfs_video.rst
      misc: mpfs_syscontroller: add functions to read device tree overlays
      board: microchip: mpfs_generic: include processing of dtbos

Randolph Lin (1):
      include: configs: andes: Remove fdt_high env variable

Vivian Wang (1):
      riscv: qemu: Remove fdt_high default

Yao Zi (7):
      configs: th1520_lpi4a: Enlarge SYS_MALLOC_F_LEN to 0x10000
      clk: thead: th1520-ap: Mark drivers as DM_FLAG_PRE_RELOC
      pinctrl: th1520: Mark driver as DM_FLAG_PRE_RELOC
      dts: th1520: Switch to upstream devicetree
      riscv: Add Kconfig options to distinguish Zaamo and Zalrsc
      configs: ibex-ast2700: Explicitly disable Zaamo and Zalrsc extension
      riscv: Add a Zalrsc-only alternative for synchronization in start.S

 arch/riscv/Kconfig                                 |  23 +-
 arch/riscv/Makefile                                |   7 +-
 arch/riscv/cpu/start.S                             |  26 +-
 arch/riscv/cpu/th1520/Kconfig                      |   1 +
 arch/riscv/dts/Makefile                            |   1 -
 arch/riscv/dts/jh7110-common-u-boot.dtsi           |  99 ---
 .../dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi  |   7 -
 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi       |   7 -
 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi    |   7 -
 .../jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi |   7 -
 .../jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi |   7 -
 ...-boot.dtsi => starfive-visionfive2-u-boot.dtsi} |  82 +--
 arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi |  10 +
 arch/riscv/dts/th1520-lichee-module-4a.dtsi        | 164 -----
 arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi     |  27 +
 arch/riscv/dts/th1520-lichee-pi-4a.dts             |  33 -
 arch/riscv/dts/th1520-u-boot.dtsi                  |  44 ++
 arch/riscv/dts/th1520.dtsi                         | 530 ---------------
 arch/riscv/include/asm/encoding.h                  |   1 -
 .../{mpfs_icicle => mpfs_generic}/Kconfig          |   6 +-
 board/microchip/mpfs_generic/MAINTAINERS           |   7 +
 .../{mpfs_icicle => mpfs_generic}/Makefile         |   2 +-
 .../mpfs_icicle.c => mpfs_generic/mpfs_generic.c}  |   2 +
 board/microchip/mpfs_icicle/MAINTAINERS            |   7 -
 board/starfive/visionfive2/spl.c                   |   3 +-
 configs/ibex-ast2700_defconfig                     |   3 +-
 ..._defconfig => microchip_mpfs_generic_defconfig} |   5 +-
 configs/starfive_visionfive2_defconfig             |   1 +
 configs/th1520_lpi4a_defconfig                     |   4 +-
 doc/board/microchip/index.rst                      |   1 +
 doc/board/microchip/mpfs_build_boot.rst            |  29 +
 doc/board/microchip/mpfs_common.rst                | 666 ++++++++++++++++++
 doc/board/microchip/mpfs_design_hss.rst            |  37 +
 doc/board/microchip/mpfs_icicle.rst                | 743 +--------------------
 doc/board/microchip/mpfs_video.rst                 | 105 +++
 drivers/clk/thead/clk-th1520-ap.c                  |   3 +
 drivers/gpio/mpfs_gpio.c                           |   8 +-
 drivers/misc/mpfs_syscontroller.c                  | 200 ++++++
 drivers/pci/pcie_starfive_jh7110.c                 |   2 -
 drivers/pinctrl/pinctrl-th1520.c                   |   1 +
 ...chip_mpfs_icicle.h => microchip_mpfs_generic.h} |   0
 include/configs/qemu-riscv.h                       |   1 -
 include/configs/voyager.h                          |   1 -
 43 files changed, 1245 insertions(+), 1675 deletions(-)
 delete mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
 rename arch/riscv/dts/{jh7110-u-boot.dtsi => starfive-visionfive2-u-boot.dtsi} (54%)
 create mode 100644 arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi
 create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts
 create mode 100644 arch/riscv/dts/th1520-u-boot.dtsi
 delete mode 100644 arch/riscv/dts/th1520.dtsi
 rename board/microchip/{mpfs_icicle => mpfs_generic}/Kconfig (92%)
 create mode 100644 board/microchip/mpfs_generic/MAINTAINERS
 rename board/microchip/{mpfs_icicle => mpfs_generic}/Makefile (85%)
 rename board/microchip/{mpfs_icicle/mpfs_icicle.c => mpfs_generic/mpfs_generic.c} (98%)
 delete mode 100644 board/microchip/mpfs_icicle/MAINTAINERS
 rename configs/{microchip_mpfs_icicle_defconfig => microchip_mpfs_generic_defconfig} (84%)
 create mode 100644 doc/board/microchip/mpfs_build_boot.rst
 create mode 100644 doc/board/microchip/mpfs_common.rst
 create mode 100644 doc/board/microchip/mpfs_design_hss.rst
 create mode 100644 doc/board/microchip/mpfs_video.rst
 rename include/configs/{microchip_mpfs_icicle.h => microchip_mpfs_generic.h} (100%)

Best regards,
Leo

Re: [GIT,PULL] u-boot-riscv/next

[Tom Rini]

On Sat, 20 Sep 2025 18:20:01 +0800, Leo Liang wrote:

> The following changes since commit a209627ed7921f40669f5c0795570d40e77e4cb7:
> 
>   Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()" (2025-09-16 16:14:30 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> [...]

Merged into u-boot/next, thanks!

-- 
Tom

Re: [GIT,PULL] u-boot-riscv/next

[E Shattow]

Hi Tom, Leo, and Yao,

On 9/20/25 10:47, Tom Rini wrote:
> On Sat, 20 Sep 2025 18:20:01 +0800, Leo Liang wrote:
> 
>> The following changes since commit a209627ed7921f40669f5c0795570d40e77e4cb7:
>>
>>   Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()" (2025-09-16 16:14:30 -0600)
>>
>> are available in the Git repository at:
>>
>>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
>>
>> [...]
> 
> Merged into u-boot/next, thanks!
> 

Runtime regression for VisionFive2 SPL bisected to bad commit
a681cfecb434 "riscv: Add a Zalrsc-only alternative for synchronization
in start.S". Confirmed by checking out origin/next (to 44c4919e9 "test:
Fix optee unit test") and reverting that commit a681cfecb434 only.

I am late to testing this, sorry about that. It would have been better
to catch this before becoming part of a range of bisect commits that now
have a non-functional SPL on visionfive2.

Best regards,

-E

Re: [GIT,PULL] u-boot-riscv/next

[E Shattow]

On 9/24/25 19:07, E Shattow wrote:
> Hi Tom, Leo, and Yao,
> 
> On 9/20/25 10:47, Tom Rini wrote:
>> On Sat, 20 Sep 2025 18:20:01 +0800, Leo Liang wrote:
>>
>>> The following changes since commit a209627ed7921f40669f5c0795570d40e77e4cb7:
>>>
>>>   Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()" (2025-09-16 16:14:30 -0600)
>>>
>>> are available in the Git repository at:
>>>
>>>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
>>>
>>> [...]
>>
>> Merged into u-boot/next, thanks!
>>
> 
> Runtime regression for VisionFive2 SPL bisected to bad commit
> a681cfecb434 "riscv: Add a Zalrsc-only alternative for synchronization
> in start.S". Confirmed by checking out origin/next (to 44c4919e9 "test:
> Fix optee unit test") and reverting that commit a681cfecb434 only.
> 
> I am late to testing this, sorry about that. It would have been better
> to catch this before becoming part of a range of bisect commits that now
> have a non-functional SPL on visionfive2.
> 
> Best regards,
> 
> -E

P.S. for Yao, there are problems with your series more than the one bad
bisect commit only. Build starfive_visionfive2_defconfig with ordinary
toolchain from Debian 13 Trixie gcc 14.2.0 and any StarFive2 (or
variant) board, to see the problem. I can't get this working with only
config changes and your series for a fixes follow-up. Too heavy of a
change... revert the series please. -E

Re: [GIT,PULL] u-boot-riscv/next

[Yao Zi]

On Wed, Sep 24, 2025 at 08:39:26PM -0700, E Shattow wrote:
> 
> On 9/24/25 19:07, E Shattow wrote:
> > Hi Tom, Leo, and Yao,
> > 
> > On 9/20/25 10:47, Tom Rini wrote:
> >> On Sat, 20 Sep 2025 18:20:01 +0800, Leo Liang wrote:
> >>
> >>> The following changes since commit a209627ed7921f40669f5c0795570d40e77e4cb7:
> >>>
> >>>   Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()" (2025-09-16 16:14:30 -0600)
> >>>
> >>> are available in the Git repository at:
> >>>
> >>>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> >>>
> >>> [...]
> >>
> >> Merged into u-boot/next, thanks!
> >>
> > 
> > Runtime regression for VisionFive2 SPL bisected to bad commit
> > a681cfecb434 "riscv: Add a Zalrsc-only alternative for synchronization
> > in start.S". Confirmed by checking out origin/next (to 44c4919e9 "test:
> > Fix optee unit test") and reverting that commit a681cfecb434 only.
> > 
> > I am late to testing this, sorry about that. It would have been better
> > to catch this before becoming part of a range of bisect commits that now
> > have a non-functional SPL on visionfive2.
> > 
> > Best regards,
> > 
> > -E
> 
> P.S. for Yao, there are problems with your series more than the one bad
> bisect commit only. Build starfive_visionfive2_defconfig with ordinary
> toolchain from Debian 13 Trixie gcc 14.2.0 and any StarFive2 (or
> variant) board, to see the problem. I can't get this working with only
> config changes and your series for a fixes follow-up. Too heavy of a
> change... revert the series please. -E

Oops, I'm okay with the revert. Should I send a series to revert the
changes?

I should really have tested this against VisonFive 2, but my board is
dead...

Best regards,
Yao Zi

Re: [GIT,PULL] u-boot-riscv/next

[E Shattow]

On 9/24/25 21:57, Yao Zi wrote:
> On Wed, Sep 24, 2025 at 08:39:26PM -0700, E Shattow wrote:
>>
>> On 9/24/25 19:07, E Shattow wrote:
>>> Hi Tom, Leo, and Yao,
>>>
>>> On 9/20/25 10:47, Tom Rini wrote:
>>>> On Sat, 20 Sep 2025 18:20:01 +0800, Leo Liang wrote:
>>>>
>>>>> The following changes since commit a209627ed7921f40669f5c0795570d40e77e4cb7:
>>>>>
>>>>>   Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()" (2025-09-16 16:14:30 -0600)
>>>>>
>>>>> are available in the Git repository at:
>>>>>
>>>>>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
>>>>>
>>>>> [...]
>>>>
>>>> Merged into u-boot/next, thanks!
>>>>
>>>
>>> Runtime regression for VisionFive2 SPL bisected to bad commit
>>> a681cfecb434 "riscv: Add a Zalrsc-only alternative for synchronization
>>> in start.S". Confirmed by checking out origin/next (to 44c4919e9 "test:
>>> Fix optee unit test") and reverting that commit a681cfecb434 only.
>>>
>>> I am late to testing this, sorry about that. It would have been better
>>> to catch this before becoming part of a range of bisect commits that now
>>> have a non-functional SPL on visionfive2.
>>>
>>> Best regards,
>>>
>>> -E
>>
>> P.S. for Yao, there are problems with your series more than the one bad
>> bisect commit only. Build starfive_visionfive2_defconfig with ordinary
>> toolchain from Debian 13 Trixie gcc 14.2.0 and any StarFive2 (or
>> variant) board, to see the problem. I can't get this working with only
>> config changes and your series for a fixes follow-up. Too heavy of a
>> change... revert the series please. -E
> 
> Oops, I'm okay with the revert. Should I send a series to revert the
> changes?
> 
> I should really have tested this against VisonFive 2, but my board is
> dead...
> 
> Best regards,
> Yao Zi

I have asked on IRC and the advice is yes, please do send a patch for
reverting, thank you. Sorry to hear about the vf2 board fail -E

[GIT PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 8e12d6ccb3cfa84dd275a1b852b2a235de0162b0:

  Merge patch series "Azure: Rework world build to directly use the container" (2025-12-07 12:53:09 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 2da2c01cd1238e210009c4aea5d429bea431754d:

  configs: starfive: enable wget https (2025-12-08 12:11:06 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/28674
----------------------------------------------------------------
- riscv: Implement private GCC library
- mpfs: Add MPFS CPU Implementation
- andes: Stop disabling device tree relocation and some minor fixes
- sifive: Stop disabling device tree relocation
- starfive: Cleanup size types and typos
----------------------------------------------------------------
Che-Wei Chuang (1):
      configs: Change default baud rate to 115200

Conor Dooley (2):
      riscv: create a custom CPU implementation for PolarFire SoC
      riscv: mpfs: move SoC level options to the CPU Kconfig

E Shattow (4):
      ram: starfive: drop references to 16GB memory size
      ram: starfive: use SZ_8G for 8GB memory size
      ram: starfive: fix typo for unsupported DDR size
      configs: starfive: enable wget https

Heinrich Schuchardt (2):
      RISC-V: implement private GCC library
      test: provide unit tests for the RISC-V private GCC library

Leo Yu-Chi Liang (1):
      riscv: cpu: Beautify the warning message

Randolph (1):
      falcon: support booting linux from MMC/Parallel Flash

Tom Rini (2):
      ae350: Stop disabling device tree relocation
      sifive-unleashed: Stop disabling device tree relocation

 arch/Kconfig                            |   1 +
 arch/riscv/Kconfig                      |   1 +
 arch/riscv/cpu/cpu.c                    |   2 +-
 arch/riscv/cpu/mpfs/Kconfig             |  33 ++++++++++
 arch/riscv/cpu/mpfs/Makefile            |   5 ++
 arch/riscv/cpu/mpfs/dram.c              |  38 ++++++++++++
 arch/riscv/dts/ae350_32.dts             |   4 +-
 arch/riscv/dts/ae350_64.dts             |   4 +-
 arch/riscv/include/asm/arch-mpfs/clk.h  |   8 +++
 arch/riscv/lib/Makefile                 |   2 +
 arch/riscv/lib/clz.c                    | 105 ++++++++++++++++++++++++++++++++
 arch/riscv/lib/ctz.c                    |  95 +++++++++++++++++++++++++++++
 board/microchip/mpfs_generic/Kconfig    |  24 +-------
 common/spl/Kconfig                      |   1 +
 configs/ae350_rv32_defconfig            |   2 +-
 configs/ae350_rv32_falcon_defconfig     |   2 +-
 configs/ae350_rv32_falcon_xip_defconfig |   5 +-
 configs/ae350_rv32_spl_defconfig        |   2 +-
 configs/ae350_rv32_spl_xip_defconfig    |   2 +-
 configs/ae350_rv32_xip_defconfig        |   2 +-
 configs/ae350_rv64_defconfig            |   2 +-
 configs/ae350_rv64_falcon_defconfig     |   2 +-
 configs/ae350_rv64_falcon_xip_defconfig |   5 +-
 configs/ae350_rv64_spl_defconfig        |   2 +-
 configs/ae350_rv64_spl_xip_defconfig    |   2 +-
 configs/ae350_rv64_xip_defconfig        |   2 +-
 configs/starfive_visionfive2_defconfig  |   2 +
 drivers/ram/starfive/ddrcsr_boot.c      |   3 -
 drivers/ram/starfive/ddrphy_start.c     |   1 -
 drivers/ram/starfive/starfive_ddr.c     |   5 +-
 drivers/ram/starfive/starfive_ddr.h     |   1 -
 include/configs/ae350.h                 |   1 -
 include/configs/sifive-unleashed.h      |   1 -
 lib/Kconfig                             |   2 +-
 test/lib/Makefile                       |   4 ++
 test/lib/test_clz.c                     |  53 ++++++++++++++++
 test/lib/test_ctz.c                     |  53 ++++++++++++++++
 37 files changed, 427 insertions(+), 52 deletions(-)
 create mode 100644 arch/riscv/cpu/mpfs/Kconfig
 create mode 100644 arch/riscv/cpu/mpfs/Makefile
 create mode 100644 arch/riscv/cpu/mpfs/dram.c
 create mode 100644 arch/riscv/include/asm/arch-mpfs/clk.h
 create mode 100644 arch/riscv/lib/clz.c
 create mode 100644 arch/riscv/lib/ctz.c
 create mode 100644 test/lib/test_clz.c
 create mode 100644 test/lib/test_ctz.c

 Best regards,
 Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

On Mon, 08 Dec 2025 14:19:25 +0800, Leo Liang wrote:

> The following changes since commit 8e12d6ccb3cfa84dd275a1b852b2a235de0162b0:
> 
>   Merge patch series "Azure: Rework world build to directly use the container" (2025-12-07 12:53:09 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> [...]

Merged into u-boot/next, thanks!

-- 
Tom

[GIT,PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 8bc2a5196c1c0bb5dbdaca073323da0015a0de37:

  arm: k3: Kconfig: Enable fTPM and RPMB support (2026-03-10 12:35:18 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 12a9c83cba29b0acf3d41fb40de6416c473c0ba3:

  riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist (2026-03-13 02:57:58 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/29497
----------------------------------------------------------------
- sifive: switch to OF_UPSTREAM
- driver: cache: Remove SiFive PL2 driver
- riscv: fixes for non-existent CONFIG
----------------------------------------------------------------
Andreas Schwab (1):
      sifive: switch to OF_UPSTREAM

Heinrich Schuchardt (3):
      riscv: don't imply non-existent CONFIG_IP_DYN
      openpiton: imply CONFIG_SPL_CPU
      riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist

Nick Hu (1):
      driver: cache: Remove SiFive PL2 driver

 arch/riscv/cpu/fu540/Kconfig                  |   1 +
 arch/riscv/cpu/fu740/Kconfig                  |   1 +
 arch/riscv/cpu/mpfs/Kconfig                   |   2 -
 arch/riscv/dts/Makefile                       |   2 -
 arch/riscv/dts/fu540-c000-u-boot.dtsi         |  16 +-
 arch/riscv/dts/fu540-c000.dtsi                | 286 ----------------------
 arch/riscv/dts/fu740-c000.dtsi                | 326 --------------------------
 arch/riscv/dts/hifive-unleashed-a00.dts       | 105 ---------
 arch/riscv/dts/hifive-unmatched-a00.dts       | 246 -------------------
 arch/riscv/lib/sifive_cache.c                 |   3 -
 board/microchip/mpfs_generic/Kconfig          |   1 -
 board/openpiton/riscv64/Kconfig               |   2 +-
 board/sifive/unleashed/Kconfig                |   1 -
 board/sifive/unmatched/Kconfig                |   1 -
 board/starfive/visionfive2/Kconfig            |   1 -
 configs/sifive_unleashed_defconfig            |   2 +-
 configs/sifive_unmatched_defconfig            |   2 +-
 drivers/cache/Kconfig                         |   6 -
 drivers/cache/Makefile                        |   1 -
 drivers/clk/sifive/fu540-prci.c               |   8 +-
 include/dt-bindings/clock/sifive-fu540-prci.h |  18 --
 21 files changed, 17 insertions(+), 1014 deletions(-)
 delete mode 100644 arch/riscv/dts/fu540-c000.dtsi
 delete mode 100644 arch/riscv/dts/fu740-c000.dtsi
 delete mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts
 delete mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
 delete mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h

 Best regards,
 Leo

Re: [GIT,PULL] u-boot-riscv/next

[Tom Rini]

On Fri, 13 Mar 2026 10:06:24 +0800, Leo Liang wrote:

> The following changes since commit 8bc2a5196c1c0bb5dbdaca073323da0015a0de37:
> 
>   arm: k3: Kconfig: Enable fTPM and RPMB support (2026-03-10 12:35:18 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> [...]

Merged into u-boot/next, thanks!

-- 
Tom

Re: [GIT,PULL] u-boot-riscv/next

[E Shattow]

Hi Leo, and Tom,

On 3/13/26 09:52, Tom Rini wrote:
> On Fri, 13 Mar 2026 10:06:24 +0800, Leo Liang wrote:
> 
>> The following changes since commit 8bc2a5196c1c0bb5dbdaca073323da0015a0de37:
>>
>>   arm: k3: Kconfig: Enable fTPM and RPMB support (2026-03-10 12:35:18 -0600)
>>
>> are available in the Git repository at:
>>
>>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
>>
>> [...]
> 
> Merged into u-boot/next, thanks!
> 

Did we get a resolution on applying Hal's series to add support for
VisionFive 2 Lite ?  ref.:
https://lore.kernel.org/u-boot/20260214145634.GQ2747538@bill-the-cat/

-E

Re: [GIT,PULL] u-boot-riscv/next

[Leo Liang]

On Fri, Mar 13, 2026 at 03:59:59PM -0700, E Shattow wrote:
> [EXTERNAL MAIL]
> 
> Hi Leo, and Tom,
> 
> On 3/13/26 09:52, Tom Rini wrote:
> > On Fri, 13 Mar 2026 10:06:24 +0800, Leo Liang wrote:
> >
> >> The following changes since commit 8bc2a5196c1c0bb5dbdaca073323da0015a0de37:
> >>
> >>   arm: k3: Kconfig: Enable fTPM and RPMB support (2026-03-10 12:35:18 -0600)
> >>
> >> are available in the Git repository at:
> >>
> >>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> >>
> >> [...]
> >
> > Merged into u-boot/next, thanks!
> >
> 
> Did we get a resolution on applying Hal's series to add support for
> VisionFive 2 Lite ?  ref.:
> https://lore.kernel.org/u-boot/20260214145634.GQ2747538@bill-the-cat/
> 
> -E

Hi E,

The previous mistake was made when resolving the conflicts.
I am preparing PRs now for all the "board support" patchsets,
and still see some minor issues.
I will send out those PRs once the issues are resolved.
Thanks for the reminder!

Best regards,
Leo

[GIT PULL] u-boot-riscv/next

[Leo Yu-Chi Liang]

Hi Tom,

The following changes since commit 841856ed9675b26ec517fdd00b5cc0aef8db508e:

  Merge patch series "Add PCIe Boot support for TI J784S4 SoC" (2026-03-16 08:24:18 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to b51e59c8b34c780e28728bc0cb58783855c7ffbf:

  riscv: Add support for BeagleV-Fire (2026-03-17 11:39:18 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/29548
----------------------------------------------------------------
- board: starfive: Add Xunlong OrangePi RV
- board: starfive: Add VisionFive 2 Lite
- board: beagle: Add BeagleV-Fire
----------------------------------------------------------------
E Shattow (5):
      board: starfive: visionfive2: Add Orange Pi RV selection by product_id
      configs: starfive: Add Orange Pi RV to visionfive2
      doc: board: starfive: Add Xunlong OrangePi RV
      doc: board: starfive: jh7110 common give build output dir by env not arg
      doc: board: starfive: jh7110 common update OPENSBI build env reference

Hal Feng (7):
      eeprom: starfive: Simplify get_ddr_size_from_eeprom()
      eeprom: starfive: Correct get_pcb_revision_from_eeprom()
      eeprom: starfive: Support eeprom data format v3
      pcie: starfive: Add a optional power gpio support
      configs: visionfive2: Add VisionFive 2 Lite DT to OF_LIST
      board: starfive: spl: Support VisionFive 2 Lite
      board: starfive: visionfive2: Add VisionFive 2 Lite fdt selection

Jamie Gibbons (1):
      riscv: Add support for BeagleV-Fire

 arch/riscv/Kconfig                                 |   4 +
 arch/riscv/cpu/jh7110/spl.c                        |   2 +-
 arch/riscv/include/asm/arch-jh7110/eeprom.h        |  13 ++-
 board/beagle/beaglev_fire/Kconfig                  |  43 ++++++++
 board/beagle/beaglev_fire/MAINTAINERS              |   7 ++
 board/beagle/beaglev_fire/Makefile                 |   6 ++
 board/beagle/beaglev_fire/beaglev_fire.c           | 117 +++++++++++++++++++++
 board/starfive/visionfive2/spl.c                   |   6 ++
 board/starfive/visionfive2/starfive_visionfive2.c  |   4 +
 .../starfive/visionfive2/visionfive2-i2c-eeprom.c  |  64 ++++++-----
 configs/beaglev_fire_defconfig                     |  29 +++++
 configs/starfive_visionfive2_defconfig             |   2 +-
 doc/board/starfive/index.rst                       |   1 +
 doc/board/starfive/jh7110_common.rst               |  11 +-
 doc/board/starfive/orangepi_rv.rst                 |  35 ++++++
 drivers/pci/pcie_starfive_jh7110.c                 |   8 ++
 include/configs/beaglev_fire.h                     |  57 ++++++++++
 17 files changed, 375 insertions(+), 34 deletions(-)
 create mode 100644 board/beagle/beaglev_fire/Kconfig
 create mode 100644 board/beagle/beaglev_fire/MAINTAINERS
 create mode 100644 board/beagle/beaglev_fire/Makefile
 create mode 100644 board/beagle/beaglev_fire/beaglev_fire.c
 create mode 100644 configs/beaglev_fire_defconfig
 create mode 100644 doc/board/starfive/orangepi_rv.rst
 create mode 100644 include/configs/beaglev_fire.h

 Best regards,
 Leo

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

On Tue, 17 Mar 2026 14:01:46 +0800, Leo Yu-Chi Liang wrote:

> The following changes since commit 841856ed9675b26ec517fdd00b5cc0aef8db508e:
> 
>   Merge patch series "Add PCIe Boot support for TI J784S4 SoC" (2026-03-16 08:24:18 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> [...]

Merged into u-boot/next, thanks!

-- 
Tom

Re: [GIT PULL] u-boot-riscv/next

[E Shattow]

Hi Tom,

There are some Fixes tags for master in this pull request applied to
next and not yet applied to master, noted inline below.

On 3/16/26 23:01, Leo Yu-Chi Liang wrote:
> Hi Tom,
> 
> The following changes since commit 841856ed9675b26ec517fdd00b5cc0aef8db508e:
> 
>   Merge patch series "Add PCIe Boot support for TI J784S4 SoC" (2026-03-16 08:24:18 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to b51e59c8b34c780e28728bc0cb58783855c7ffbf:
> 
>   riscv: Add support for BeagleV-Fire (2026-03-17 11:39:18 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/29548
> ----------------------------------------------------------------
> - board: starfive: Add Xunlong OrangePi RV
> - board: starfive: Add VisionFive 2 Lite
> - board: beagle: Add BeagleV-Fire
> ----------------------------------------------------------------
> E Shattow (5):
>       board: starfive: visionfive2: Add Orange Pi RV selection by product_id
>       configs: starfive: Add Orange Pi RV to visionfive2
>       doc: board: starfive: Add Xunlong OrangePi RV

>       doc: board: starfive: jh7110 common give build output dir by env not arg

commit 24662f698f5ad6f444e6dc437c0b5a932726a6ef
Fixes: 8304f3226700 ("doc: board: starfive: update jh7110 common
description")

>       doc: board: starfive: jh7110 common update OPENSBI build env reference

commit 1edeb52086c6e160d93d86386505e6cc6ce1457c
Fixes: 8304f3226700 ("doc: board: starfive: update jh7110 common
description")

> 
> Hal Feng (7):
>       eeprom: starfive: Simplify get_ddr_size_from_eeprom()

commit 6015c98be50f2fc571c294d2f2b0768212fb7e99
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")

>       eeprom: starfive: Correct get_pcb_revision_from_eeprom()

commit 78253aeeecdfea4c71779905ff2b400fa7400b1c
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")

>       eeprom: starfive: Support eeprom data format v3
>       pcie: starfive: Add a optional power gpio support
>       configs: visionfive2: Add VisionFive 2 Lite DT to OF_LIST
>       board: starfive: spl: Support VisionFive 2 Lite
>       board: starfive: visionfive2: Add VisionFive 2 Lite fdt selection
> 
> Jamie Gibbons (1):
>       riscv: Add support for BeagleV-Fire
> 
>  arch/riscv/Kconfig                                 |   4 +
>  arch/riscv/cpu/jh7110/spl.c                        |   2 +-
>  arch/riscv/include/asm/arch-jh7110/eeprom.h        |  13 ++-
>  board/beagle/beaglev_fire/Kconfig                  |  43 ++++++++
>  board/beagle/beaglev_fire/MAINTAINERS              |   7 ++
>  board/beagle/beaglev_fire/Makefile                 |   6 ++
>  board/beagle/beaglev_fire/beaglev_fire.c           | 117 +++++++++++++++++++++
>  board/starfive/visionfive2/spl.c                   |   6 ++
>  board/starfive/visionfive2/starfive_visionfive2.c  |   4 +
>  .../starfive/visionfive2/visionfive2-i2c-eeprom.c  |  64 ++++++-----
>  configs/beaglev_fire_defconfig                     |  29 +++++
>  configs/starfive_visionfive2_defconfig             |   2 +-
>  doc/board/starfive/index.rst                       |   1 +
>  doc/board/starfive/jh7110_common.rst               |  11 +-
>  doc/board/starfive/orangepi_rv.rst                 |  35 ++++++
>  drivers/pci/pcie_starfive_jh7110.c                 |   8 ++
>  include/configs/beaglev_fire.h                     |  57 ++++++++++
>  17 files changed, 375 insertions(+), 34 deletions(-)
>  create mode 100644 board/beagle/beaglev_fire/Kconfig
>  create mode 100644 board/beagle/beaglev_fire/MAINTAINERS
>  create mode 100644 board/beagle/beaglev_fire/Makefile
>  create mode 100644 board/beagle/beaglev_fire/beaglev_fire.c
>  create mode 100644 configs/beaglev_fire_defconfig
>  create mode 100644 doc/board/starfive/orangepi_rv.rst
>  create mode 100644 include/configs/beaglev_fire.h
> 
>  Best regards,
>  Leo

I note that there may be other authors' contributions applied to next
with Fixes tags for master that are not part of this pull request, not
highlighted in my reply here.

Thanks,

-E

Re: [GIT PULL] u-boot-riscv/next

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 5181 bytes --]

On Mon, Mar 23, 2026 at 12:20:02PM -0700, E Shattow wrote:
> Hi Tom,
> 
> There are some Fixes tags for master in this pull request applied to
> next and not yet applied to master, noted inline below.
> 
> On 3/16/26 23:01, Leo Yu-Chi Liang wrote:
> > Hi Tom,
> > 
> > The following changes since commit 841856ed9675b26ec517fdd00b5cc0aef8db508e:
> > 
> >   Merge patch series "Add PCIe Boot support for TI J784S4 SoC" (2026-03-16 08:24:18 -0600)
> > 
> > are available in the Git repository at:
> > 
> >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > 
> > for you to fetch changes up to b51e59c8b34c780e28728bc0cb58783855c7ffbf:
> > 
> >   riscv: Add support for BeagleV-Fire (2026-03-17 11:39:18 +0800)
> > 
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/29548
> > ----------------------------------------------------------------
> > - board: starfive: Add Xunlong OrangePi RV
> > - board: starfive: Add VisionFive 2 Lite
> > - board: beagle: Add BeagleV-Fire
> > ----------------------------------------------------------------
> > E Shattow (5):
> >       board: starfive: visionfive2: Add Orange Pi RV selection by product_id
> >       configs: starfive: Add Orange Pi RV to visionfive2
> >       doc: board: starfive: Add Xunlong OrangePi RV
> 
> >       doc: board: starfive: jh7110 common give build output dir by env not arg
> 
> commit 24662f698f5ad6f444e6dc437c0b5a932726a6ef
> Fixes: 8304f3226700 ("doc: board: starfive: update jh7110 common
> description")
> 
> >       doc: board: starfive: jh7110 common update OPENSBI build env reference
> 
> commit 1edeb52086c6e160d93d86386505e6cc6ce1457c
> Fixes: 8304f3226700 ("doc: board: starfive: update jh7110 common
> description")
> 
> > 
> > Hal Feng (7):
> >       eeprom: starfive: Simplify get_ddr_size_from_eeprom()
> 
> commit 6015c98be50f2fc571c294d2f2b0768212fb7e99
> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
> 
> >       eeprom: starfive: Correct get_pcb_revision_from_eeprom()
> 
> commit 78253aeeecdfea4c71779905ff2b400fa7400b1c
> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
> 
> >       eeprom: starfive: Support eeprom data format v3
> >       pcie: starfive: Add a optional power gpio support
> >       configs: visionfive2: Add VisionFive 2 Lite DT to OF_LIST
> >       board: starfive: spl: Support VisionFive 2 Lite
> >       board: starfive: visionfive2: Add VisionFive 2 Lite fdt selection
> > 
> > Jamie Gibbons (1):
> >       riscv: Add support for BeagleV-Fire
> > 
> >  arch/riscv/Kconfig                                 |   4 +
> >  arch/riscv/cpu/jh7110/spl.c                        |   2 +-
> >  arch/riscv/include/asm/arch-jh7110/eeprom.h        |  13 ++-
> >  board/beagle/beaglev_fire/Kconfig                  |  43 ++++++++
> >  board/beagle/beaglev_fire/MAINTAINERS              |   7 ++
> >  board/beagle/beaglev_fire/Makefile                 |   6 ++
> >  board/beagle/beaglev_fire/beaglev_fire.c           | 117 +++++++++++++++++++++
> >  board/starfive/visionfive2/spl.c                   |   6 ++
> >  board/starfive/visionfive2/starfive_visionfive2.c  |   4 +
> >  .../starfive/visionfive2/visionfive2-i2c-eeprom.c  |  64 ++++++-----
> >  configs/beaglev_fire_defconfig                     |  29 +++++
> >  configs/starfive_visionfive2_defconfig             |   2 +-
> >  doc/board/starfive/index.rst                       |   1 +
> >  doc/board/starfive/jh7110_common.rst               |  11 +-
> >  doc/board/starfive/orangepi_rv.rst                 |  35 ++++++
> >  drivers/pci/pcie_starfive_jh7110.c                 |   8 ++
> >  include/configs/beaglev_fire.h                     |  57 ++++++++++
> >  17 files changed, 375 insertions(+), 34 deletions(-)
> >  create mode 100644 board/beagle/beaglev_fire/Kconfig
> >  create mode 100644 board/beagle/beaglev_fire/MAINTAINERS
> >  create mode 100644 board/beagle/beaglev_fire/Makefile
> >  create mode 100644 board/beagle/beaglev_fire/beaglev_fire.c
> >  create mode 100644 configs/beaglev_fire_defconfig
> >  create mode 100644 doc/board/starfive/orangepi_rv.rst
> >  create mode 100644 include/configs/beaglev_fire.h
> > 
> >  Best regards,
> >  Leo
> 
> I note that there may be other authors' contributions applied to next
> with Fixes tags for master that are not part of this pull request, not
> highlighted in my reply here.

Thanks for looking at this. To be clear and to repeat what I said on
IRC, we don't have the formal process (nor tooling nor human backup)
that the linux kernel has about fixes tags and what they get applied to.
It's up to individual custodians to decide if a Fixes commit is worth
pushing to a pending release, once the next window is open, or holding
off for more testing, as it's not serious enough of a problem. That
means it's also up to a contributor to follow-up if they thought
something should really go to master instead (and custodians should be
uinsg b4 and b4 ty, so contributors know where something is applied,
once it is applied).

-- 
Tom

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