From: Leo Liang <ycliang@andestech.com>
To: Bo Gan <ganboing@gmail.com>
Cc: <rick@andestech.com>, <trini@konsulko.com>,
<yanhong.wang@starfivetech.com>, <minda.chen@starfivetech.com>,
<duwe@suse.de>, <namcao@linutronix.de>,
<xingyu.wu@starfivetech.com>, <mason.huo@starfivetech.com>,
<hal.feng@starfivetech.com>, <chanho61.park@samsung.com>,
<u-boot@lists.denx.de>
Subject: Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
Date: Tue, 12 Mar 2024 13:12:13 +0800 [thread overview]
Message-ID: <Ze_kLShwfoZ8TS88@swlinux02> (raw)
In-Reply-To: <1709694011-683-1-git-send-email-ganboing@gmail.com>
On Tue, Mar 05, 2024 at 07:00:11PM -0800, Bo Gan wrote:
> Previously PLL node was missing from SPL dts. This caused BUS_ROOT
> to stay on OSC clock (24Mhz). As a result, all peripherals have to
> run at a much lower frequency, and loading from sdcard/emmc is slow.
> Thus, enabling PLL node in dts to fix this.
>
> Signed-off-by: Bo Gan <ganboing@gmail.com>
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2024-03-12 5:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 3:00 [PATCH] riscv: dts: jh7110: Enable PLL node in SPL Bo Gan
2024-03-12 5:12 ` Leo Liang [this message]
2024-03-12 6:09 ` Hal Feng
2024-04-10 1:55 ` E Shattow
2024-04-10 6:44 ` Bo Gan
2024-04-17 4:59 ` E Shattow
2024-04-20 0:51 ` Bo Gan
2024-04-20 10:56 ` E Shattow
2024-07-11 19:55 ` E Shattow
2024-07-16 10:59 ` Leo Liang
2024-07-19 10:52 ` E Shattow
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