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* [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
@ 2024-02-22 14:52 thomas.perrot
  2024-03-12  5:23 ` Leo Liang
  0 siblings, 1 reply; 2+ messages in thread
From: thomas.perrot @ 2024-02-22 14:52 UTC (permalink / raw)
  To: u-boot; +Cc: Thomas Perrot

From: Thomas Perrot <thomas.perrot@bootlin.com>

It appears that there is some timing marginality either in the
board layout or the SoC that results in occasional data corruption
on some boards.
We observed this issue on some of the new HiFive Unmatched RevB
boards during volume production as well as some of the original
HiFive Unmatched boards from 2021 in our possession. This means
that there are other boards out there that might have the issue
too.

We have done some limited testing with DDR4 at 1600MT/s and
faulty boards (failing at 1866MT/s) passed.
We plan further testing after we procure a temperature chamber.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
---
 arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 706224b384d2..956237c3218e 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -77,7 +77,7 @@
 			       0x0 0x100b2000 0x0 0x2000
 			       0x0 0x100b8000 0x0 0x1000>;
 			clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
-			clock-frequency = <933333324>;
+			clock-frequency = <800000004>;
 			bootph-pre-ram;
 		};
 	};
-- 
2.43.2


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
  2024-02-22 14:52 [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s thomas.perrot
@ 2024-03-12  5:23 ` Leo Liang
  0 siblings, 0 replies; 2+ messages in thread
From: Leo Liang @ 2024-03-12  5:23 UTC (permalink / raw)
  To: thomas.perrot; +Cc: u-boot

On Thu, Feb 22, 2024 at 03:52:03PM +0100, thomas.perrot@bootlin.com wrote:
> From: Thomas Perrot <thomas.perrot@bootlin.com>
> 
> It appears that there is some timing marginality either in the
> board layout or the SoC that results in occasional data corruption
> on some boards.
> We observed this issue on some of the new HiFive Unmatched RevB
> boards during volume production as well as some of the original
> HiFive Unmatched boards from 2021 in our possession. This means
> that there are other boards out there that might have the issue
> too.
> 
> We have done some limited testing with DDR4 at 1600MT/s and
> faulty boards (failing at 1866MT/s) passed.
> We plan further testing after we procure a temperature chamber.
> 
> Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
> ---
>  arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2024-03-12  5:24 UTC | newest]

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2024-02-22 14:52 [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s thomas.perrot
2024-03-12  5:23 ` Leo Liang

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