From: Leo Liang <ycliang@andestech.com>
To: Kongyang Liu <seashell11234455@gmail.com>
Cc: <u-boot@lists.denx.de>, Rick Chen <rick@andestech.com>,
Tom Rini <trini@konsulko.com>
Subject: Re: [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b
Date: Tue, 12 Mar 2024 17:44:19 +0800 [thread overview]
Message-ID: <ZfAj8z9quBmKFf-K@swlinux02> (raw)
In-Reply-To: <20240309165533.48795-3-seashell11234455@gmail.com>
On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote:
> Add dcache operations invalidate_dcache_range and flush_dcache_range for
> cv1800b.
>
> Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
> ---
>
> (no changes since v1)
>
> arch/riscv/cpu/cv1800b/Makefile | 1 +
> arch/riscv/cpu/cv1800b/cache.c | 45 +++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 arch/riscv/cpu/cv1800b/cache.c
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2024-03-12 9:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-09 16:54 [PATCH v2 0/2] riscv: cpu: Add support for cv1800b SoC Kongyang Liu
2024-03-09 16:54 ` [PATCH v2 1/2] riscv: cpu: cv1800b: " Kongyang Liu
2024-03-12 9:42 ` Leo Liang
2024-03-09 16:54 ` [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b Kongyang Liu
2024-03-12 9:44 ` Leo Liang [this message]
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