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Date: Tue, 12 Mar 2024 17:44:19 +0800
From: Leo Liang <ycliang@andestech.com>
To: Kongyang Liu <seashell11234455@gmail.com>
CC: <u-boot@lists.denx.de>, Rick Chen <rick@andestech.com>, Tom Rini
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Subject: Re: [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b
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On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote:
> Add dcache operations invalidate_dcache_range and flush_dcache_range for
> cv1800b.
> 
> Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
> ---
> 
> (no changes since v1)
> 
>  arch/riscv/cpu/cv1800b/Makefile |  1 +
>  arch/riscv/cpu/cv1800b/cache.c  | 45 +++++++++++++++++++++++++++++++++
>  2 files changed, 46 insertions(+)
>  create mode 100644 arch/riscv/cpu/cv1800b/cache.c

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>