From: Leo Liang <ycliang@andestech.com>
To: Kongyang Liu <seashell11234455@gmail.com>
Cc: <u-boot@lists.denx.de>, Anup Patel <anup@brainfault.org>,
Bin Meng <bmeng@tinylab.org>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Michal Simek <michal.simek@amd.com>,
Randolph <randolph@andestech.com>, Rick Chen <rick@andestech.com>,
Samuel Holland <samuel@sholland.org>,
Shengyu Qu <wiagn233@outlook.com>, Tom Rini <trini@konsulko.com>,
Yu Chien Peter Lin <peterlin@andestech.com>
Subject: Re: [PATCH v2 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC
Date: Tue, 12 Mar 2024 17:42:34 +0800 [thread overview]
Message-ID: <ZfAjinoWTrQ6bt2j@swlinux02> (raw)
In-Reply-To: <20240309165533.48795-2-seashell11234455@gmail.com>
On Sun, Mar 10, 2024 at 12:54:56AM +0800, Kongyang Liu wrote:
> Add Sophgo cv1800b SoC to support RISC-V arch.
>
> Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
> ---
>
> Changes in v2:
> - Remove duplicate code in function cleanup_before_linux
>
> arch/riscv/Kconfig | 1 +
> arch/riscv/cpu/cv1800b/Kconfig | 12 ++++++++++++
> arch/riscv/cpu/cv1800b/Makefile | 6 ++++++
> arch/riscv/cpu/cv1800b/cpu.c | 9 +++++++++
> arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++++++++
> board/sophgo/milkv_duo/Kconfig | 4 ++--
> 6 files changed, 51 insertions(+), 2 deletions(-)
> create mode 100644 arch/riscv/cpu/cv1800b/Kconfig
> create mode 100644 arch/riscv/cpu/cv1800b/Makefile
> create mode 100644 arch/riscv/cpu/cv1800b/cpu.c
> create mode 100644 arch/riscv/cpu/cv1800b/dram.c
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2024-03-12 9:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-09 16:54 [PATCH v2 0/2] riscv: cpu: Add support for cv1800b SoC Kongyang Liu
2024-03-09 16:54 ` [PATCH v2 1/2] riscv: cpu: cv1800b: " Kongyang Liu
2024-03-12 9:42 ` Leo Liang [this message]
2024-03-09 16:54 ` [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b Kongyang Liu
2024-03-12 9:44 ` Leo Liang
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