From: Leo Liang <ycliang@andestech.com>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Rick Chen <rick@andestech.com>,
Sean Anderson <sean.anderson@seco.com>,
Andre Przywara <andre.przywara@arm.com>, <u-boot@lists.denx.de>
Subject: Re: [PATCH 1/1] riscv: semihosting: correct alignment
Date: Mon, 8 Jul 2024 19:58:16 +0800 [thread overview]
Message-ID: <ZovUWPTTmP57g-Sk@swlinux02> (raw)
In-Reply-To: <20240619152252.173684-1-heinrich.schuchardt@canonical.com>
On Wed, Jun 19, 2024 at 05:22:52PM +0200, Heinrich Schuchardt wrote:
> Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file") reduced the alignment of function smh_trap().
>
> As described in the "RISC-V Semihosting" specification [1] the ssli,
> ebreak, and srai statements must all reside in the same memory page.
>
> [1] RISC-V Semihosting, Version 0.4, 12th June 2024
> https://github.com/riscv-non-isa/riscv-semihosting
>
> Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> arch/riscv/lib/semihosting.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2024-07-08 11:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 15:22 [PATCH 1/1] riscv: semihosting: correct alignment Heinrich Schuchardt
2024-07-08 11:58 ` Leo Liang [this message]
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