* [PATCH 1/1] riscv: semihosting: correct alignment
@ 2024-06-19 15:22 Heinrich Schuchardt
2024-07-08 11:58 ` Leo Liang
0 siblings, 1 reply; 2+ messages in thread
From: Heinrich Schuchardt @ 2024-06-19 15:22 UTC (permalink / raw)
To: Rick Chen, Leo; +Cc: Sean Anderson, Andre Przywara, u-boot, Heinrich Schuchardt
Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
assembly file") reduced the alignment of function smh_trap().
As described in the "RISC-V Semihosting" specification [1] the ssli,
ebreak, and srai statements must all reside in the same memory page.
[1] RISC-V Semihosting, Version 0.4, 12th June 2024
https://github.com/riscv-non-isa/riscv-semihosting
Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
arch/riscv/lib/semihosting.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/semihosting.S b/arch/riscv/lib/semihosting.S
index c0c571bce9b..49bb419a962 100644
--- a/arch/riscv/lib/semihosting.S
+++ b/arch/riscv/lib/semihosting.S
@@ -8,7 +8,7 @@
.pushsection .text.smh_trap, "ax"
ENTRY(smh_trap)
- .align 2
+ .align 4 /* keep slli, ebreak, srai in same page */
.option push
.option norvc /* semihosting sequence must be 32-bit wide */
--
2.45.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH 1/1] riscv: semihosting: correct alignment
2024-06-19 15:22 [PATCH 1/1] riscv: semihosting: correct alignment Heinrich Schuchardt
@ 2024-07-08 11:58 ` Leo Liang
0 siblings, 0 replies; 2+ messages in thread
From: Leo Liang @ 2024-07-08 11:58 UTC (permalink / raw)
To: Heinrich Schuchardt; +Cc: Rick Chen, Sean Anderson, Andre Przywara, u-boot
On Wed, Jun 19, 2024 at 05:22:52PM +0200, Heinrich Schuchardt wrote:
> Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file") reduced the alignment of function smh_trap().
>
> As described in the "RISC-V Semihosting" specification [1] the ssli,
> ebreak, and srai statements must all reside in the same memory page.
>
> [1] RISC-V Semihosting, Version 0.4, 12th June 2024
> https://github.com/riscv-non-isa/riscv-semihosting
>
> Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> arch/riscv/lib/semihosting.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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