[GIT PULL] u-boot-riscv/master

[Leo Liang <ycliang@andestech.com>]

Hi Tom,

The following changes since commit 5024a96db8ea6ff2e814f4599af9e5faf09296b7:

  Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into dts/upstream (2024-07-20 11:15:22 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to dd3cd9eecc9846e7c37a97c9755d2a83fb995cbb:

  Revert "riscv: dts: jh7110: Enable PLL node in SPL" (2024-07-22 15:42:07 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/21724
----------------------------------------------------------------
Andreas Schwab (1):
      board: sifive: unmatched: remove extra space in fdtfile value

Heinrich Schuchardt (2):
      riscv: add RISC-V fields to bdinfo command
      riscv: semihosting: correct alignment

Leo Yu-Chi Liang (1):
      Revert "riscv: dts: jh7110: Enable PLL node in SPL"

 arch/riscv/dts/jh7110-u-boot.dtsi    |  4 ----
 arch/riscv/lib/Makefile              |  1 +
 arch/riscv/lib/bdinfo.c              | 18 ++++++++++++++++++
 arch/riscv/lib/semihosting.S         |  2 +-
 board/sifive/unmatched/unmatched.env |  2 +-
 5 files changed, 21 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/lib/bdinfo.c

Best regards,
Leo