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* [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
@ 2024-03-06  3:00 Bo Gan
  2024-03-12  5:12 ` Leo Liang
  2024-03-12  6:09 ` Hal Feng
  0 siblings, 2 replies; 11+ messages in thread
From: Bo Gan @ 2024-03-06  3:00 UTC (permalink / raw)
  To: rick, ycliang, trini, yanhong.wang, minda.chen, duwe, namcao,
	xingyu.wu, mason.huo, hal.feng, chanho61.park, u-boot

Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan <ganboing@gmail.com>
---
 arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 2f560e7..c09d5c9 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -93,6 +93,10 @@
 	bootph-pre-ram;
 };
 
+&pllclk {
+	bootph-pre-ram;
+};
+
 &S7_0 {
 	status = "okay";
 };
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2024-07-19 10:57 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-06  3:00 [PATCH] riscv: dts: jh7110: Enable PLL node in SPL Bo Gan
2024-03-12  5:12 ` Leo Liang
2024-03-12  6:09 ` Hal Feng
2024-04-10  1:55   ` E Shattow
2024-04-10  6:44     ` Bo Gan
2024-04-17  4:59       ` E Shattow
2024-04-20  0:51         ` Bo Gan
2024-04-20 10:56           ` E Shattow
2024-07-11 19:55             ` E Shattow
2024-07-16 10:59               ` Leo Liang
2024-07-19 10:52                 ` E Shattow

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