From: Leo Liang <ycliang@andestech.com>
To: Jacky Chou <jacky_chou@aspeedtech.com>
Cc: <ryan_chen@aspeedtech.com>, <chiawei_wang@aspeedtech.com>,
<BMC-SW@aspeedtech.com>, <joel@jms.id.au>,
<joe.hershberger@ni.com>, <rfried.dev@gmail.com>,
<trini@konsulko.com>, <sjg@chromium.org>, <kobedylan@gmail.com>,
<u-boot@lists.denx.de>
Subject: Re: [PATCH] net: ftgmac100: Fixed the cache coherency issues of rx memory
Date: Mon, 9 Sep 2024 15:48:20 +0800 [thread overview]
Message-ID: <Zt6oRBmYjgXmIQJz@swlinux02> (raw)
In-Reply-To: <20240627062600.3142388-1-jacky_chou@aspeedtech.com>
On Thu, Jun 27, 2024 at 02:26:00PM +0800, Jacky Chou wrote:
> When executing TFTP, the ARP will be replied to after receiving
> the ARP. U-boot's ARP routine modifies the data in the receive
> packet in response to the ARP packet and then copies it
> into the transmit packet.
> At this point, the received packet cache is inconsistent.
> It is possible that the cache will perform a writeback action to
> affect the MAC receiving packets.
>
> Avoid the same problem that occurs in other networking protocols.
> In the free_pkt function, ensure cache and memory consistency.
>
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
> drivers/net/ftgmac100.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2024-09-09 7:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 6:26 [PATCH] net: ftgmac100: Fixed the cache coherency issues of rx memory Jacky Chou
2024-09-09 7:48 ` Leo Liang [this message]
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