[PULL] u-boot-riscv/next

[PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

Please pull u-boot-riscv/next into -next.

The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94:

  Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400)

are available in the Git repository at:

  git@source.denx.de:u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208:

  test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856

----------------------------------------------------------------
Bin Meng (6):
      riscv: ae350: dts: Add SPDX license header
      riscv: ae350: dts: Remove the unnecessary space in bootargs
      riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
      riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
      riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
      riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT

Sean Anderson (11):
      clk: Allow force setting clock defaults before relocation
      clk: k210: Rewrite to remove CCF
      clk: k210: Move pll into the rest of the driver
      clk: k210: Implement soc_clk_dump
      clk: k210: Re-add support for setting rate
      clk: k210: Don't set PLL rates if we are already at the correct rate
      clk: k210: Remove bypass driver
      clk: k210: Move k210 clock out of its own subdirectory
      k210: dts: Set PLL1 to the same rate as PLL0
      k210: Don't imply CCF
      test: Add K210 PLL tests to sandbox defconfigs

 MAINTAINERS                             |    4 +-
 arch/riscv/dts/ae350-u-boot.dtsi        |   52 ++
 arch/riscv/dts/ae350_32.dts             |    9 +-
 arch/riscv/dts/ae350_64.dts             |    7 +-
 arch/riscv/dts/k210.dtsi                |    2 +
 board/sipeed/maix/Kconfig               |    2 -
 configs/sandbox64_defconfig             |    2 +
 configs/sandbox_defconfig               |    2 +
 configs/sandbox_flattree_defconfig      |    2 +
 configs/sipeed_maix_bitm_defconfig      |    2 +-
 doc/board/AndesTech/ax25-ae350.rst      |   19 +-
 drivers/clk/Kconfig                     |   14 +-
 drivers/clk/Makefile                    |    2 +-
 drivers/clk/clk-uclass.c                |   27 +-
 drivers/clk/clk_kendryte.c              | 1320 +++++++++++++++++++++++++++++++
 drivers/clk/kendryte/Kconfig            |   12 -
 drivers/clk/kendryte/Makefile           |    1 -
 drivers/clk/kendryte/bypass.c           |  273 -------
 drivers/clk/kendryte/clk.c              |  668 ----------------
 drivers/clk/kendryte/pll.c              |  585 --------------
 drivers/clk/rockchip/clk_rk3308.c       |    2 +-
 drivers/core/device.c                   |    2 +-
 drivers/net/gmac_rockchip.c             |    2 +-
 include/clk.h                           |   30 +-
 include/dt-bindings/clock/k210-sysctl.h |   94 ++-
 include/kendryte/bypass.h               |   31 -
 include/kendryte/clk.h                  |   35 -
 include/kendryte/pll.h                  |   34 -
 28 files changed, 1502 insertions(+), 1733 deletions(-)
 create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi
 create mode 100644 drivers/clk/clk_kendryte.c
 delete mode 100644 drivers/clk/kendryte/Kconfig
 delete mode 100644 drivers/clk/kendryte/Makefile
 delete mode 100644 drivers/clk/kendryte/bypass.c
 delete mode 100644 drivers/clk/kendryte/clk.c
 delete mode 100644 drivers/clk/kendryte/pll.c
 delete mode 100644 include/kendryte/bypass.h
 delete mode 100644 include/kendryte/clk.h

 Best regards,
 Leo

Re: [PULL] u-boot-riscv/next

[Bin Meng]

Hi Leo,

On Wed, Jun 16, 2021 at 3:44 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Tom,
>
> Please pull u-boot-riscv/next into -next.
>
> The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94:
>
>   Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400)
>
> are available in the Git repository at:
>
>   git@source.denx.de:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208:
>
>   test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856
>
> ----------------------------------------------------------------
> Bin Meng (6):
>       riscv: ae350: dts: Add SPDX license header
>       riscv: ae350: dts: Remove the unnecessary space in bootargs
>       riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
>       riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
>       riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
>       riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT

It seems this patch is missing?

riscv: andes_plic: Fix riscv_get_ipi() mask
http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng.cn@gmail.com/

Regards,
Bin

Re: [PULL] u-boot-riscv/next

[Leo Liang]

On Wed, Jun 16, 2021 at 04:07:26PM +0800, Bin Meng wrote:
> Hi Leo,
> 
> On Wed, Jun 16, 2021 at 3:44 PM Leo Liang <ycliang@andestech.com> wrote:
> >
> > Hi Tom,
> >
> > Please pull u-boot-riscv/next into -next.
> >
> > The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94:
> >
> >   Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400)
> >
> > are available in the Git repository at:
> >
> >   git@source.denx.de:u-boot/custodians/u-boot-riscv.git
> >
> > for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208:
> >
> >   test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800)
> >
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856
> >
> > ----------------------------------------------------------------
> > Bin Meng (6):
> >       riscv: ae350: dts: Add SPDX license header
> >       riscv: ae350: dts: Remove the unnecessary space in bootargs
> >       riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
> >       riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
> >       riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
> >       riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
> 
> It seems this patch is missing?
> 
> riscv: andes_plic: Fix riscv_get_ipi() mask
> http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng.cn@gmail.com/
> 
> Regards,
> Bin

Hi Bin,

Sorry, I must have omitted it by accident.

Hi Tom,

Could you drop this PR ?
I will send another one including the patch Bin mentioned.
Thanks!

Best regards,
Leo

Re: [PULL] u-boot-riscv/next

[Tom Rini]

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On Wed, Jun 16, 2021 at 04:28:21PM +0800, Leo Liang wrote:
> On Wed, Jun 16, 2021 at 04:07:26PM +0800, Bin Meng wrote:
> > Hi Leo,
> > 
> > On Wed, Jun 16, 2021 at 3:44 PM Leo Liang <ycliang@andestech.com> wrote:
> > >
> > > Hi Tom,
> > >
> > > Please pull u-boot-riscv/next into -next.
> > >
> > > The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94:
> > >
> > >   Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > >   git@source.denx.de:u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208:
> > >
> > >   test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856
> > >
> > > ----------------------------------------------------------------
> > > Bin Meng (6):
> > >       riscv: ae350: dts: Add SPDX license header
> > >       riscv: ae350: dts: Remove the unnecessary space in bootargs
> > >       riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
> > >       riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
> > >       riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
> > >       riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
> > 
> > It seems this patch is missing?
> > 
> > riscv: andes_plic: Fix riscv_get_ipi() mask
> > http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng.cn@gmail.com/
> > 
> > Regards,
> > Bin
> 
> Hi Bin,
> 
> Sorry, I must have omitted it by accident.
> 
> Hi Tom,
> 
> Could you drop this PR ?
> I will send another one including the patch Bin mentioned.
> Thanks!

Will do.

-- 
Tom

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[PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 435596d57f8beedf36b5dc858fe7ba9d6c03334b:

  Merge tag 'u-boot-imx-20220922' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-09-22 10:29:29 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 3c1ec13317292933fd01d9c60aae3ff1d5bc171e:

  riscv: ae350: Disable AVAILABLE_HARTS (2022-09-26 14:29:44 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13595

----------------------------------------------------------------
Nikita Shubin (1):
      spl: introduce SPL_XIP to config

Rick Chen (2):
      riscv: Introduce AVAILABLE_HARTS
      riscv: ae350: Disable AVAILABLE_HARTS

 arch/riscv/Kconfig                   | 14 ++++++++++++++
 arch/riscv/cpu/cpu.c                 |  4 +++-
 arch/riscv/cpu/start.S               | 17 ++++++++++-------
 arch/riscv/include/asm/global_data.h |  4 +++-
 arch/riscv/lib/asm-offsets.c         |  4 +++-
 arch/riscv/lib/smp.c                 |  4 +++-
 configs/ae350_rv32_spl_defconfig     |  1 +
 configs/ae350_rv32_spl_xip_defconfig |  2 +-
 configs/ae350_rv64_spl_defconfig     |  1 +
 configs/ae350_rv64_spl_xip_defconfig |  2 +-
 10 files changed, 40 insertions(+), 13 deletions(-)

Best regards,
Leo

Re: [PULL] u-boot-riscv/next

[Tom Rini]

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On Mon, Sep 26, 2022 at 07:39:22AM +0000, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit 435596d57f8beedf36b5dc858fe7ba9d6c03334b:
> 
>   Merge tag 'u-boot-imx-20220922' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-09-22 10:29:29 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to 3c1ec13317292933fd01d9c60aae3ff1d5bc171e:
> 
>   riscv: ae350: Disable AVAILABLE_HARTS (2022-09-26 14:29:44 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13595
> 

Applied to u-boot/next, thanks!

-- 
Tom

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[PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit c58ee1c9946a1550b1f6fee2b25da9ecc89baf71:

  Merge branch '2023-09-19-tidy-up-some-kconfig-options' into next (2023-09-19 17:44:18 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 90602e779d3ae3bd02faae0eb40b4fcefec419f7:

  riscv: dts: starfive: generate u-boot-spl.bin.normal.out (2023-09-20 21:05:16 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17779
----------------------------------------------------------------

+ Add NVMe & USB boot devices for VisionFive2
+ Add StarFive SPL image support in mkimage tool

----------------------------------------------------------------
Heinrich Schuchardt (4):
      riscv: set fdtfile on VisionFive 2
      configs: NVMe/USB target boot devices on VisionFive 2
      tools: mkimage: Add StarFive SPL image support
      riscv: dts: starfive: generate u-boot-spl.bin.normal.out

Milan P. Stanić (1):
      starfive: visionfive2: add mmc0 and nvme boot targets

 arch/riscv/Kconfig                                 |   1 +
 .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi   |  11 ++
 board/starfive/visionfive2/starfive_visionfive2.c  |  43 ++++-
 boot/image.c                                       |   1 +
 doc/board/starfive/visionfive2.rst                 |  14 +-
 include/configs/starfive-visionfive2.h             |   3 +
 include/image.h                                    |   1 +
 tools/Makefile                                     |   1 +
 tools/sfspl.c                                      | 174 +++++++++++++++++++++
 9 files changed, 235 insertions(+), 14 deletions(-)
 create mode 100644 tools/sfspl.c

 Best regards,
 Leo

Re: [PULL] u-boot-riscv/next

[Tom Rini]

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On Thu, Sep 21, 2023 at 09:28:46AM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit c58ee1c9946a1550b1f6fee2b25da9ecc89baf71:
> 
>   Merge branch '2023-09-19-tidy-up-some-kconfig-options' into next (2023-09-19 17:44:18 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to 90602e779d3ae3bd02faae0eb40b4fcefec419f7:
> 
>   riscv: dts: starfive: generate u-boot-spl.bin.normal.out (2023-09-20 21:05:16 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17779

Applied to u-boot/next, thanks!

-- 
Tom

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[PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit 78d898eec080b02059c8dc09318b8761044fea85:

  Merge patch series "phycore-am62/4: Add more boot sources" (2024-09-10 14:56:12 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 2db018d2ca5ebd7acc717f0b1959ee67fcd2b0a1:

  configs: ibex-ast2700: Enable DRAM and timer driver (2024-09-11 20:35:04 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315
----------------------------------------------------------------
- Aspeed: Add AST2700 board (Ibex RISC-V core) support
	- Add timer, dram controller, network support
- Sophgo: Add clock controller support for Milk-V Duo
----------------------------------------------------------------
Chia-Wei Wang (8):
      riscv: Make A ISA extension selectable
      riscv: Make stack size shift configurable
      riscv: u-boot-spl.lds: Remove _image_binary_end alignment
      riscv: Add AST2700 SoC initial platform support
      timer: Add AST2700 IBEX timer support
      board: ibex_ast2700: Add FMC header support
      ram: ast2700: Add DRAM controller initialization
      configs: ibex-ast2700: Enable DRAM and timer driver

Jacky Chou (5):
      net: ftgmac100: Fixed the cache coherency issues of rx memory
      net: ftgmac100: Fixed NC-SI PHY device cannot get
      net: ftgmac100: Modify desc. size to cache line
      net: ftgmac100: Add Aspeed AST2700 support
      driver: net: Add Aspeed AST2700 MDIO support

Kongyang Liu (4):
      dt-bindings: clk: import header for clock controller of sophgo CV1800B
      clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC
      configs: milkv_duo: Enable clock controller
      riscv: dts: sophgo: Replace device clocks with real clocks.

 arch/riscv/Kconfig                                 |   12 +-
 arch/riscv/cpu/ast2700/Kconfig                     |    6 +
 arch/riscv/cpu/ast2700/Makefile                    |    1 +
 arch/riscv/cpu/ast2700/cpu.c                       |   23 +
 arch/riscv/cpu/u-boot-spl.lds                      |    2 -
 arch/riscv/dts/Makefile                            |    1 +
 arch/riscv/dts/ast2700-ibex.dts                    |   22 +
 arch/riscv/dts/ast2700-u-boot.dtsi                 |   40 +
 arch/riscv/dts/ast2700.dtsi                        |   76 +
 arch/riscv/dts/cv18xx.dtsi                         |   40 +-
 arch/riscv/include/asm/arch-ast2700/fmc_hdr.h      |   52 +
 arch/riscv/include/asm/arch-ast2700/scu.h          |  145 +
 arch/riscv/include/asm/arch-ast2700/sdram.h        |  137 +
 arch/riscv/include/asm/arch-ast2700/sli.h          |   82 +
 board/aspeed/ibex_ast2700/Kconfig                  |   21 +
 board/aspeed/ibex_ast2700/MAINTAINERS              |    7 +
 board/aspeed/ibex_ast2700/Makefile                 |    3 +
 board/aspeed/ibex_ast2700/fmc_hdr.c                |   64 +
 board/aspeed/ibex_ast2700/ibex_ast2700.c           |   85 +
 board/aspeed/ibex_ast2700/sli.c                    |   72 +
 configs/ibex-ast2700_defconfig                     |   94 +
 configs/milkv_duo_defconfig                        |    3 +-
 doc/board/aspeed/ibex-ast2700.rst                  |   26 +
 doc/board/aspeed/index.rst                         |    9 +
 doc/board/index.rst                                |    1 +
 drivers/clk/Kconfig                                |    1 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/sophgo/Kconfig                         |   14 +
 drivers/clk/sophgo/Makefile                        |    6 +
 drivers/clk/sophgo/clk-common.h                    |   74 +
 drivers/clk/sophgo/clk-cv1800b.c                   |  754 +++
 drivers/clk/sophgo/clk-cv1800b.h                   |  123 +
 drivers/clk/sophgo/clk-ip.c                        |  594 ++
 drivers/clk/sophgo/clk-ip.h                        |  288 +
 drivers/clk/sophgo/clk-pll.c                       |  275 +
 drivers/clk/sophgo/clk-pll.h                       |   74 +
 drivers/net/aspeed_mdio.c                          |    1 +
 drivers/net/ftgmac100.c                            |   89 +-
 drivers/net/ftgmac100.h                            |   17 +-
 drivers/ram/Makefile                               |    2 +-
 drivers/ram/aspeed/Kconfig                         |   27 +-
 drivers/ram/aspeed/Makefile                        |    1 +
 .../dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c  | 2700 ++++++++
 .../dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c  | 6930 ++++++++++++++++++++
 drivers/ram/aspeed/sdram_ast2700.c                 | 1036 +++
 drivers/timer/Kconfig                              |    6 +
 drivers/timer/Makefile                             |    1 +
 drivers/timer/ast_ibex_timer.c                     |   45 +
 include/configs/ibex_ast2700.h                     |   12 +
 include/dt-bindings/clock/sophgo,cv1800.h          |  176 +
 50 files changed, 14220 insertions(+), 51 deletions(-)
 create mode 100644 arch/riscv/cpu/ast2700/Kconfig
 create mode 100644 arch/riscv/cpu/ast2700/Makefile
 create mode 100644 arch/riscv/cpu/ast2700/cpu.c
 create mode 100644 arch/riscv/dts/ast2700-ibex.dts
 create mode 100644 arch/riscv/dts/ast2700-u-boot.dtsi
 create mode 100644 arch/riscv/dts/ast2700.dtsi
 create mode 100644 arch/riscv/include/asm/arch-ast2700/fmc_hdr.h
 create mode 100644 arch/riscv/include/asm/arch-ast2700/scu.h
 create mode 100644 arch/riscv/include/asm/arch-ast2700/sdram.h
 create mode 100644 arch/riscv/include/asm/arch-ast2700/sli.h
 create mode 100644 board/aspeed/ibex_ast2700/Kconfig
 create mode 100644 board/aspeed/ibex_ast2700/MAINTAINERS
 create mode 100644 board/aspeed/ibex_ast2700/Makefile
 create mode 100644 board/aspeed/ibex_ast2700/fmc_hdr.c
 create mode 100644 board/aspeed/ibex_ast2700/ibex_ast2700.c
 create mode 100644 board/aspeed/ibex_ast2700/sli.c
 create mode 100644 configs/ibex-ast2700_defconfig
 create mode 100644 doc/board/aspeed/ibex-ast2700.rst
 create mode 100644 doc/board/aspeed/index.rst
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-common.h
 create mode 100644 drivers/clk/sophgo/clk-cv1800b.c
 create mode 100644 drivers/clk/sophgo/clk-cv1800b.h
 create mode 100644 drivers/clk/sophgo/clk-ip.c
 create mode 100644 drivers/clk/sophgo/clk-ip.h
 create mode 100644 drivers/clk/sophgo/clk-pll.c
 create mode 100644 drivers/clk/sophgo/clk-pll.h
 create mode 100644 drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c
 create mode 100644 drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c
 create mode 100644 drivers/ram/aspeed/sdram_ast2700.c
 create mode 100644 drivers/timer/ast_ibex_timer.c
 create mode 100644 include/configs/ibex_ast2700.h
 create mode 100644 include/dt-bindings/clock/sophgo,cv1800.h


Best regards,
Leo

Re: [PULL] u-boot-riscv/next

[Tom Rini]

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On Thu, Sep 12, 2024 at 02:39:24PM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit 78d898eec080b02059c8dc09318b8761044fea85:
> 
>   Merge patch series "phycore-am62/4: Add more boot sources" (2024-09-10 14:56:12 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to 2db018d2ca5ebd7acc717f0b1959ee67fcd2b0a1:
> 
>   configs: ibex-ast2700: Enable DRAM and timer driver (2024-09-11 20:35:04 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315

Applied to u-boot/next, thanks!

-- 
Tom

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[PULL] u-boot-riscv/next

[Leo Liang]

Hi Tom,

The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:

  Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02 08:43:10 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to b911af6d60d3be570469b92df751874dc376336b:

  MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-03 14:17:46 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26483
----------------------------------------------------------------
- board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
- RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
- driver: Add SD card support to the Beagle-V-Fire
- MAINTAINERS: Add Yao Zi as maintainer for th1520
----------------------------------------------------------------
Eoin Dickson (2):
      gpio: add PolarFire SoC GPIO and Core GPIO driver
      spi: coreqspi: add xfer function for PolarFire SoC

Heinrich Schuchardt (1):
      configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V

Yao Zi (6):
      riscv: cpu: th1520: Build spl.c for SPL only
      riscv: cpu: th1520: Support cache enabling/disabling in M mode only
      riscv: dts: th1520: Prepare binman configuration for loading OpenSBI
      board: thead: licheepi4a: Run proper U-Boot in S-Mode
      doc: thead: lpi4a: Update for S-Mode proper U-Boot support
      MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer

 MAINTAINERS                             |   7 ++
 arch/riscv/cpu/th1520/Makefile          |   2 +-
 arch/riscv/cpu/th1520/cache.c           |   2 +
 arch/riscv/dts/thead-th1520-binman.dtsi |  32 +++++-
 common/spl/Kconfig                      |   2 +-
 configs/starfive_visionfive2_defconfig  |   1 -
 configs/th1520_lpi4a_defconfig          |   2 +-
 configs/xilinx_mbv32_defconfig          |   1 -
 configs/xilinx_mbv32_smode_defconfig    |   1 -
 configs/xilinx_mbv64_defconfig          |   1 -
 configs/xilinx_mbv64_smode_defconfig    |   1 -
 doc/board/thead/lpi4a.rst               | 125 ++++++--------------
 drivers/gpio/Kconfig                    |   5 +
 drivers/gpio/Makefile                   |   1 +
 drivers/gpio/mpfs_gpio.c                | 198 ++++++++++++++++++++++++++++++++
 drivers/spi/microchip_coreqspi.c        | 113 +++++++++++++++++-
 16 files changed, 391 insertions(+), 103 deletions(-)
 create mode 100644 drivers/gpio/mpfs_gpio.c

Best regards,
Leo

Re: [PULL] u-boot-riscv/next

[Tom Rini]

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On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:
> 
>   Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02 08:43:10 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> 
> for you to fetch changes up to b911af6d60d3be570469b92df751874dc376336b:
> 
>   MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-03 14:17:46 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26483
> ----------------------------------------------------------------
> - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
> - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
> - driver: Add SD card support to the Beagle-V-Fire
> - MAINTAINERS: Add Yao Zi as maintainer for th1520
> ----------------------------------------------------------------

This introduces a failure to build on microchip_mpfs_icicle currently in
-next.

-- 
Tom

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Re: [PULL] u-boot-riscv/next

[Yao Zi]

On Thu, Jun 05, 2025 at 02:05:06PM -0600, Tom Rini wrote:
> On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:
> 
> > Hi Tom,
> > 
> > The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:
> > 
> >   Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02 08:43:10 -0600)
> > 
> > are available in the Git repository at:
> > 
> >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > 
> > for you to fetch changes up to b911af6d60d3be570469b92df751874dc376336b:
> > 
> >   MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-03 14:17:46 +0800)
> > 
> > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26483
> > ----------------------------------------------------------------
> > - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
> > - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
> > - driver: Add SD card support to the Beagle-V-Fire
> > - MAINTAINERS: Add Yao Zi as maintainer for th1520
> > ----------------------------------------------------------------
> 
> This introduces a failure to build on microchip_mpfs_icicle currently in
> -next.

microchip_mpfs_icicle_defconfig fails to build in u-boot-riscv/next as
well. Reverting b73971dea9fed ("spi: coreqspi: add xfer function for
PolarFire SoC") fixes it.

Seems the patch doesn't adapt the multiple-cs-capable definition of
dm_slave_plat, which was introduced in commit 34da258bb04 ("spi:
spi-uclass: Read chipselect and restrict capabilities") in the last
year. Thus I doubt whether the patch has been built and tested against a
recent version of U-Boot.


> -- 
> Tom

Regards,
Yao Zi

Re: [PULL] u-boot-riscv/next

[Leo Liang]

On Sun, Jun 08, 2025 at 02:37:04AM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
> 
> On Thu, Jun 05, 2025 at 02:05:06PM -0600, Tom Rini wrote:
> > On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
> > > The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:
> > >
> > >   Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02 08:43:10 -0600)
> > >
> > > are available in the Git repository at:
> > >
> > >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > >
> > > for you to fetch changes up to b911af6d60d3be570469b92df751874dc376336b:
> > >
> > >   MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-03 14:17:46 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26483
> > > ----------------------------------------------------------------
> > > - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
> > > - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
> > > - driver: Add SD card support to the Beagle-V-Fire
> > > - MAINTAINERS: Add Yao Zi as maintainer for th1520
> > > ----------------------------------------------------------------
> >
> > This introduces a failure to build on microchip_mpfs_icicle currently in
> > -next.
> 
> microchip_mpfs_icicle_defconfig fails to build in u-boot-riscv/next as
> well. Reverting b73971dea9fed ("spi: coreqspi: add xfer function for
> PolarFire SoC") fixes it.
> 
> Seems the patch doesn't adapt the multiple-cs-capable definition of
> dm_slave_plat, which was introduced in commit 34da258bb04 ("spi:
> spi-uclass: Read chipselect and restrict capabilities") in the last
> year. Thus I doubt whether the patch has been built and tested against a
> recent version of U-Boot.
> 

Sorry for the negligence.
I will respin a PR for next and 
ask the submitter to send a fixed patch set.

Best regards,
Leo

> > --
> > Tom
> 
> Regards,
> Yao Zi

Re: [PULL] u-boot-riscv/next

[Leo Liang]

On Sun, Jun 08, 2025 at 02:37:04AM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
> 
> On Thu, Jun 05, 2025 at 02:05:06PM -0600, Tom Rini wrote:
> > On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
> > > The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:
> > >
> > >   Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02 08:43:10 -0600)
> > >
> > > are available in the Git repository at:
> > >
> > >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > >
> > > for you to fetch changes up to b911af6d60d3be570469b92df751874dc376336b:
> > >
> > >   MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-03 14:17:46 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26483
> > > ----------------------------------------------------------------
> > > - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
> > > - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
> > > - driver: Add SD card support to the Beagle-V-Fire
> > > - MAINTAINERS: Add Yao Zi as maintainer for th1520
> > > ----------------------------------------------------------------
> >
> > This introduces a failure to build on microchip_mpfs_icicle currently in
> > -next.
> 
> microchip_mpfs_icicle_defconfig fails to build in u-boot-riscv/next as
> well. Reverting b73971dea9fed ("spi: coreqspi: add xfer function for
> PolarFire SoC") fixes it.
> 
> Seems the patch doesn't adapt the multiple-cs-capable definition of
> dm_slave_plat, which was introduced in commit 34da258bb04 ("spi:
> spi-uclass: Read chipselect and restrict capabilities") in the last
> year. Thus I doubt whether the patch has been built and tested against a
> recent version of U-Boot.
> 

Hi Eoin,

Your patch ("spi: coreqspi: add xfer function for PolarFire SoC")[1] does not pass CI[2].

Could you fix this issue and resend a V3?

Best regards,
Leo

[1] https://patchwork.ozlabs.org/project/uboot/patch/20250529102112.3544972-3-Eoin.Dickson@microchip.com/
[2] https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/1155749#L5205
> 
> > --
> > Tom
> 
> Regards,
> Yao Zi