* [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support
@ 2010-08-26 21:05 tmarri at apm.com
2010-08-27 9:01 ` Stefan Roese
0 siblings, 1 reply; 4+ messages in thread
From: tmarri at apm.com @ 2010-08-26 21:05 UTC (permalink / raw)
To: u-boot
From: Tirumala Marri <tmarri@apm.com>
APM82XXX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.
Signed-off-by: Tirumala R Marri <tmarri@apm.com>
---
arch/powerpc/cpu/ppc4xx/cpu.c | 35 +++++++++++++++++++++++++++++++--
arch/powerpc/cpu/ppc4xx/cpu_init.c | 9 ++++---
arch/powerpc/cpu/ppc4xx/start.S | 10 +++++++-
arch/powerpc/include/asm/processor.h | 1 +
4 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 851065c..5fe5d8c 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -80,7 +80,8 @@ static int pci_async_enabled(void)
#endif /* CONFIG_PCI */
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
- !defined(CONFIG_405) && !defined(CONFIG_405EX)
+ !defined(CONFIG_405) && !defined(CONFIG_405EX) && \
+ !defined(CONFIG_APM82XXX)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
@@ -250,6 +251,21 @@ static char *bootstrap_str[] = {
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
+#if defined(CONFIG_APM82XXX)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "NAND (8 bits)",
+ "NOR (8 bits)",
+ "NOR (8 bits) w/PLL Bypassed",
+ "I2C (Addr 0x54)",
+ "I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
+
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
@@ -285,7 +301,7 @@ int checkcpu (void)
uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM82XXX)
u32 reg;
#endif
@@ -304,6 +320,8 @@ int checkcpu (void)
#if defined(CONFIG_XILINX_440)
puts("IBM PowerPC 4");
+#elif defined(CONFIG_APM82XXX)
+ puts("APM PowerPC APM82");
#else
puts("AMCC PowerPC 4");
#endif
@@ -316,7 +334,7 @@ int checkcpu (void)
#if defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
puts("60");
-#else
+#elif !defined(CONFIG_APM82XXX)
puts("40");
#endif
#endif
@@ -598,7 +616,18 @@ int checkcpu (void)
puts("GX Rev. A");
strcpy(addstr, "No Security support");
break;
+#if defined(CONFIG_APM82XXX)
+ case PVR_APM82XXX_RA:
+ mfsdr(SDR0_ECID3, reg);
+ if (reg & 0x00200000)
+ puts("181 Rev. A");
+ if (reg & 0x00100000)
+ strcpy(addstr, "No Security support");
+ else
+ strcpy(addstr, "Security support");
+ break;
+#endif
case PVR_VIRTEX5:
puts("x5 VIRTEX5");
break;
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index c04eede..2308051 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_PLL_RECONFIG
#define CONFIG_SYS_PLL_RECONFIG 0
#endif
-
#if defined(CONFIG_440EPX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
static void reset_with_rli(void)
@@ -222,13 +221,15 @@ void reconfigure_pll(u32 new_cpu_freq)
void
cpu_init_f (void)
{
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) ||\
+ defined(CONFIG_460EX) || defined(CONFIG_APM82XXX)
u32 val;
#endif
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined(CONFIG_405EX)) && \
+ !defined(CONFIG_SYS_4xx_GPIO_TABLE) && !defined(CONFIG_APM82XXX)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
@@ -384,7 +385,7 @@ cpu_init_f (void)
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 5296dad..9cb818d 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -700,7 +700,8 @@ _start:
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460SX)
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_APM82XXX)
lis r1, 0x0000
ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
mtdcr L2_CACHE_CFG,r1
@@ -728,7 +729,8 @@ _start:
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) ||\
+ defined(CONFIG_460GT) || defined(CONFIG_APM82XXX)
lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr ISRAM0_SB0CR,r1
@@ -752,7 +754,11 @@ _start:
mtdcr ISRAM1_PMEG,r1
lis r1,0x0004 /* BAS = 4_0004_0000 */
+#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */
+ ori r1,r1,0x0784 /* 32k */
+#else
ori r1,r1,0x0984 /* 64k */
+#endif
mtdcr ISRAM1_SB0CR,r1
#endif
#elif defined(CONFIG_460SX)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 84a1e2e..c58492d 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -916,6 +916,7 @@
#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
+#define PVR_APM82XXX_RA 0x12C41C80 /* APM82XXX rev A */
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
--
1.6.1.rc3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support
2010-08-26 21:05 [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support tmarri at apm.com
@ 2010-08-27 9:01 ` Stefan Roese
2010-08-27 9:20 ` Stefan Roese
2010-08-30 17:17 ` Tirumala Marri
0 siblings, 2 replies; 4+ messages in thread
From: Stefan Roese @ 2010-08-27 9:01 UTC (permalink / raw)
To: u-boot
Hi Marri,
On Thursday 26 August 2010 23:05:44 tmarri at apm.com wrote:
> From: Tirumala Marri <tmarri@apm.com>
>
> APM82XXX is a new line of SoCs which are derivatives of
> PPC44X family of processors. This patch adds support of CPU, cache,
> tlb, 32k ocm, bootstraps, PLB and AHB bus.
Thanks. General comment: Please add me on Cc on these PPC4xx
related patches. More comments below.
> Signed-off-by: Tirumala R Marri <tmarri@apm.com>
> ---
> arch/powerpc/cpu/ppc4xx/cpu.c | 35
> +++++++++++++++++++++++++++++++-- arch/powerpc/cpu/ppc4xx/cpu_init.c |
> 9 ++++---
> arch/powerpc/cpu/ppc4xx/start.S | 10 +++++++-
> arch/powerpc/include/asm/processor.h | 1 +
> 4 files changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
> index 851065c..5fe5d8c 100644
> --- a/arch/powerpc/cpu/ppc4xx/cpu.c
> +++ b/arch/powerpc/cpu/ppc4xx/cpu.c
> @@ -80,7 +80,8 @@ static int pci_async_enabled(void)
> #endif /* CONFIG_PCI */
>
> #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
> - !defined(CONFIG_405) && !defined(CONFIG_405EX)
> + !defined(CONFIG_405) && !defined(CONFIG_405EX) && \
> + !defined(CONFIG_APM82XXX)
> int pci_arbiter_enabled(void)
> {
> #if defined(CONFIG_405GP)
> @@ -250,6 +251,21 @@ static char *bootstrap_str[] = {
> };
> static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
> #endif
> +#if defined(CONFIG_APM82XXX)
> +#define SDR0_PINSTP_SHIFT 29
> +static char *bootstrap_str[] = {
> + "RESERVED",
> + "RESERVED",
> + "RESERVED",
> + "NAND (8 bits)",
> + "NOR (8 bits)",
> + "NOR (8 bits) w/PLL Bypassed",
> + "I2C (Addr 0x54)",
> + "I2C (Addr 0x52)",
> +};
> +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
> +#endif
> +
>
> #if defined(SDR0_PINSTP_SHIFT)
> static int bootstrap_option(void)
> @@ -285,7 +301,7 @@ int checkcpu (void)
> uint pvr = get_pvr();
> ulong clock = gd->cpu_clk;
> char buf[32];
> -#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
> +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) ||
> defined(CONFIG_APM82XXX) u32 reg;
> #endif
>
> @@ -304,6 +320,8 @@ int checkcpu (void)
>
> #if defined(CONFIG_XILINX_440)
> puts("IBM PowerPC 4");
> +#elif defined(CONFIG_APM82XXX)
> + puts("APM PowerPC APM82");
> #else
> puts("AMCC PowerPC 4");
> #endif
> @@ -316,7 +334,7 @@ int checkcpu (void)
> #if defined(CONFIG_440)
> #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
> puts("60");
> -#else
> +#elif !defined(CONFIG_APM82XXX)
> puts("40");
> #endif
> #endif
> @@ -598,7 +616,18 @@ int checkcpu (void)
> puts("GX Rev. A");
> strcpy(addstr, "No Security support");
> break;
> +#if defined(CONFIG_APM82XXX)
> + case PVR_APM82XXX_RA:
> + mfsdr(SDR0_ECID3, reg);
> + if (reg & 0x00200000)
> + puts("181 Rev. A");
>
> + if (reg & 0x00100000)
> + strcpy(addstr, "No Security support");
> + else
> + strcpy(addstr, "Security support");
> + break;
> +#endif
> case PVR_VIRTEX5:
> puts("x5 VIRTEX5");
> break;
> diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c
> b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..2308051 100644
> --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
> +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
> @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
> #ifndef CONFIG_SYS_PLL_RECONFIG
> #define CONFIG_SYS_PLL_RECONFIG 0
> #endif
> -
Why did you remove this empty line?
Please fix and resubmit. Thanks.
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support
2010-08-27 9:01 ` Stefan Roese
@ 2010-08-27 9:20 ` Stefan Roese
2010-08-30 17:17 ` Tirumala Marri
1 sibling, 0 replies; 4+ messages in thread
From: Stefan Roese @ 2010-08-27 9:20 UTC (permalink / raw)
To: u-boot
Hi Marri,
On Friday 27 August 2010 11:01:56 Stefan Roese wrote:
> > APM82XXX is a new line of SoCs which are derivatives of
> > PPC44X family of processors. This patch adds support of CPU, cache,
> > tlb, 32k ocm, bootstraps, PLB and AHB bus.
>
> Thanks. General comment: Please add me on Cc on these PPC4xx
> related patches. More comments below.
Another general comment: The email address "open-source-review at apm.com"
doesn't seem to be public accessible. Please fix or remove from further mails.
Thanks.
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support
2010-08-27 9:01 ` Stefan Roese
2010-08-27 9:20 ` Stefan Roese
@ 2010-08-30 17:17 ` Tirumala Marri
1 sibling, 0 replies; 4+ messages in thread
From: Tirumala Marri @ 2010-08-30 17:17 UTC (permalink / raw)
To: u-boot
Stefan,
Thanks for the review. I will fix accordingly.
Regards,
Marri
> -----Original Message-----
> From: Stefan Roese [mailto:sr at denx.de]
> Sent: Friday, August 27, 2010 2:02 AM
> To: u-boot at lists.denx.de
> Cc: tmarri at apm.com; open-source-review at apm.com
> Subject: Re: [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support
>
> Hi Marri,
>
> On Thursday 26 August 2010 23:05:44 tmarri at apm.com wrote:
> > From: Tirumala Marri <tmarri@apm.com>
> >
> > APM82XXX is a new line of SoCs which are derivatives of
> > PPC44X family of processors. This patch adds support of CPU, cache,
> > tlb, 32k ocm, bootstraps, PLB and AHB bus.
>
> Thanks. General comment: Please add me on Cc on these PPC4xx
> related patches. More comments below.
>
> > Signed-off-by: Tirumala R Marri <tmarri@apm.com>
> > ---
> > arch/powerpc/cpu/ppc4xx/cpu.c | 35
> > +++++++++++++++++++++++++++++++-- arch/powerpc/cpu/ppc4xx/cpu_init.c
> |
> > 9 ++++---
> > arch/powerpc/cpu/ppc4xx/start.S | 10 +++++++-
> > arch/powerpc/include/asm/processor.h | 1 +
> > 4 files changed, 46 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c
> b/arch/powerpc/cpu/ppc4xx/cpu.c
> > index 851065c..5fe5d8c 100644
> > --- a/arch/powerpc/cpu/ppc4xx/cpu.c
> > +++ b/arch/powerpc/cpu/ppc4xx/cpu.c
> > @@ -80,7 +80,8 @@ static int pci_async_enabled(void)
> > #endif /* CONFIG_PCI */
> >
> > #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
> > - !defined(CONFIG_405) && !defined(CONFIG_405EX)
> > + !defined(CONFIG_405) && !defined(CONFIG_405EX) && \
> > + !defined(CONFIG_APM82XXX)
> > int pci_arbiter_enabled(void)
> > {
> > #if defined(CONFIG_405GP)
> > @@ -250,6 +251,21 @@ static char *bootstrap_str[] = {
> > };
> > static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F',
> 'H' };
> > #endif
> > +#if defined(CONFIG_APM82XXX)
> > +#define SDR0_PINSTP_SHIFT 29
> > +static char *bootstrap_str[] = {
> > + "RESERVED",
> > + "RESERVED",
> > + "RESERVED",
> > + "NAND (8 bits)",
> > + "NOR (8 bits)",
> > + "NOR (8 bits) w/PLL Bypassed",
> > + "I2C (Addr 0x54)",
> > + "I2C (Addr 0x52)",
> > +};
> > +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G',
> 'H' };
> > +#endif
> > +
> >
> > #if defined(SDR0_PINSTP_SHIFT)
> > static int bootstrap_option(void)
> > @@ -285,7 +301,7 @@ int checkcpu (void)
> > uint pvr = get_pvr();
> > ulong clock = gd->cpu_clk;
> > char buf[32];
> > -#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
> > +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) ||
> > defined(CONFIG_APM82XXX) u32 reg;
> > #endif
> >
> > @@ -304,6 +320,8 @@ int checkcpu (void)
> >
> > #if defined(CONFIG_XILINX_440)
> > puts("IBM PowerPC 4");
> > +#elif defined(CONFIG_APM82XXX)
> > + puts("APM PowerPC APM82");
> > #else
> > puts("AMCC PowerPC 4");
> > #endif
> > @@ -316,7 +334,7 @@ int checkcpu (void)
> > #if defined(CONFIG_440)
> > #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
> > puts("60");
> > -#else
> > +#elif !defined(CONFIG_APM82XXX)
> > puts("40");
> > #endif
> > #endif
> > @@ -598,7 +616,18 @@ int checkcpu (void)
> > puts("GX Rev. A");
> > strcpy(addstr, "No Security support");
> > break;
> > +#if defined(CONFIG_APM82XXX)
> > + case PVR_APM82XXX_RA:
> > + mfsdr(SDR0_ECID3, reg);
> > + if (reg & 0x00200000)
> > + puts("181 Rev. A");
> >
> > + if (reg & 0x00100000)
> > + strcpy(addstr, "No Security support");
> > + else
> > + strcpy(addstr, "Security support");
> > + break;
> > +#endif
> > case PVR_VIRTEX5:
> > puts("x5 VIRTEX5");
> > break;
> > diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c
> > b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..2308051 100644
> > --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
> > +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
> > @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
> > #ifndef CONFIG_SYS_PLL_RECONFIG
> > #define CONFIG_SYS_PLL_RECONFIG 0
> > #endif
> > -
>
> Why did you remove this empty line?
>
> Please fix and resubmit. Thanks.
>
> Cheers,
> Stefan
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email:
> office at denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2010-08-30 17:17 UTC | newest]
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2010-08-26 21:05 [U-Boot] [PATCH 1/8] APM82xxx: Add CPU support tmarri at apm.com
2010-08-27 9:01 ` Stefan Roese
2010-08-27 9:20 ` Stefan Roese
2010-08-30 17:17 ` Tirumala Marri
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