Re: Build for RISC-V with LLVM

[Yao Zi <ziyao@disroot.org>]

On Fri, Apr 25, 2025 at 12:43:08PM -0500, Nathaniel Hourt wrote:
> Hi, all
> 
> I am trying to build u-boot and SPL for my Mars board (riscv, variant of the
> starfive visionfive2) following the board-specific docs [1], using
> LLVM/clang as my toolchain with the HOSTCC and CC make options mentioned in
> [2]. I'm building from a RISC-V native chroot using qemu-binfmt so I am not
> using the cross-compile options; thus my make invocation looks like `make
> HOSTCC=clang CC=clang` (for OpenSBI, I just pass 'LLVM=1'). Note that the
> chroot I'm building from does not contain gcc/binutils at all; LLVM is the
> only toolchain present.
> 
> The build usually succeeds, so I try to pass the SPL to the MaskROM over
> UART (using the u-boot-spl.bin.normal.out image) and it just hangs. No
> output, no response, and I have to reset the board. If I pass a working SPL

Have you tried to apply this patch[1]? U-Boot support for JH7110 is
broken at least in v2025.04 release afaik.

Best regards,
Yao Zi

[1]: https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schuchardt@canonical.com/

> I downloaded, it logs some output then accepts a main u-boot payload over
> UART, so if I send the main u-boot payload I built (u-boot.itb), I get a
> "Load address misaligned" error as in [3].
> 
> I attempted to configure my SPL to log to UART by turning on various logging
> options in `menuconfig`, including the options recently mentioned by
> Heinrich Schuchardt in [4], but I have been unsuccessful in getting any
> output from the SPL I built.
> 
> So I am looking for guidance. Is building with LLVM/clang (for riscv)
> supported? I don't know what to try next.
> 
> Thanks
> —
> Nathaniel
> 
> 
> [1]
> https://docs.u-boot.org/en/latest/board/starfive/milk-v_mars.html#milk-v-mars
> [2] https://docs.u-boot.org/en/latest/build/clang.html
> [3] https://pastebin.com/xwEcqEpz
> [4] https://lists.denx.de/pipermail/u-boot/2025-April/586264.html