From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1BCEC3ABC3 for ; Mon, 12 May 2025 18:15:11 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3640D80C83; Mon, 12 May 2025 20:15:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id AF03E826AA; Mon, 12 May 2025 20:15:08 +0200 (CEST) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9C6B180584 for ; Mon, 12 May 2025 20:15:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTPS id 54CIEm7j069859 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Tue, 13 May 2025 02:14:48 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02 (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 13 May 2025 02:14:48 +0800 Date: Tue, 13 May 2025 02:14:45 +0800 From: Leo Liang To: E Shattow CC: Rick Chen , Minda Chen , Hal Feng , Tom Rini , Subject: Re: [PATCH] riscv: starfive: jh7110: move uart0 clock frequency to config header Message-ID: References: <20250503115301.972550-1-e@freeshell.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250503115301.972550-1-e@freeshell.de> User-Agent: Mutt/2.2.10 (e0e92c31) (2023-03-25) X-Originating-IP: [10.0.15.183] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 54CIEm7j069859 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Sat, May 03, 2025 at 04:52:52AM -0700, E Shattow wrote: > Move unnecessary clock frequency assignment out of device-tree and into the > board config header so that the ns16550 serial driver can successfully init > during SPL after failing to resolve the parent clock from upstream dts. The > serial driver will then resolve clock frequency from device-tree node parent > clock at init during Main app as it is expected by upstream. > > Signed-off-by: E Shattow > --- > arch/riscv/dts/jh7110-common-u-boot.dtsi | 1 - > include/configs/starfive-visionfive2.h | 2 ++ > 2 files changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang