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From: Leo Liang <ycliang@andestech.com>
To: <Eoin.Dickson@microchip.com>
Cc: Tom Rini <trini@konsulko.com>, <u-boot@lists.denx.de>,
	<rick@andestech.com>, Yao Zi <ziyao@disroot.org>
Subject: Re: [PULL] u-boot-riscv/next
Date: Mon, 30 Jun 2025 20:02:27 +0800	[thread overview]
Message-ID: <aGJ803txDE1mbYjj@swlinux02> (raw)
In-Reply-To: <aET27PdD0VwuzOAB@pie>

On Sun, Jun 08, 2025 at 02:37:04AM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
> 
> On Thu, Jun 05, 2025 at 02:05:06PM -0600, Tom Rini wrote:
> > On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
> > > The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:
> > >
> > >   Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02 08:43:10 -0600)
> > >
> > > are available in the Git repository at:
> > >
> > >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
> > >
> > > for you to fetch changes up to b911af6d60d3be570469b92df751874dc376336b:
> > >
> > >   MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-03 14:17:46 +0800)
> > >
> > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26483
> > > ----------------------------------------------------------------
> > > - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot
> > > - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB
> > > - driver: Add SD card support to the Beagle-V-Fire
> > > - MAINTAINERS: Add Yao Zi as maintainer for th1520
> > > ----------------------------------------------------------------
> >
> > This introduces a failure to build on microchip_mpfs_icicle currently in
> > -next.
> 
> microchip_mpfs_icicle_defconfig fails to build in u-boot-riscv/next as
> well. Reverting b73971dea9fed ("spi: coreqspi: add xfer function for
> PolarFire SoC") fixes it.
> 
> Seems the patch doesn't adapt the multiple-cs-capable definition of
> dm_slave_plat, which was introduced in commit 34da258bb04 ("spi:
> spi-uclass: Read chipselect and restrict capabilities") in the last
> year. Thus I doubt whether the patch has been built and tested against a
> recent version of U-Boot.
> 

Hi Eoin,

Your patch ("spi: coreqspi: add xfer function for PolarFire SoC")[1] does not pass CI[2].

Could you fix this issue and resend a V3?

Best regards,
Leo

[1] https://patchwork.ozlabs.org/project/uboot/patch/20250529102112.3544972-3-Eoin.Dickson@microchip.com/
[2] https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/1155749#L5205
> 
> > --
> > Tom
> 
> Regards,
> Yao Zi

  parent reply	other threads:[~2025-06-30 12:03 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-03  6:45 [PULL] u-boot-riscv/next Leo Liang
2025-06-05 20:05 ` Tom Rini
2025-06-08  2:37   ` Yao Zi
2025-06-09  8:04     ` Leo Liang
2025-06-30 12:02     ` Leo Liang [this message]
  -- strict thread matches above, loose matches on Subject: below --
2024-09-12  6:39 Leo Liang
2024-09-12 17:44 ` Tom Rini
2023-09-21  1:28 Leo Liang
2023-09-21 19:56 ` Tom Rini
2022-09-26  7:39 Leo Liang
2022-09-27 12:53 ` Tom Rini
2021-06-16  7:44 Leo Liang
2021-06-16  8:07 ` Bin Meng
2021-06-16  8:28   ` Leo Liang
2021-06-16 12:06     ` Tom Rini

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