Re: [PATCH v3 12/12] timer: p8700: Add support for reading time from memory-mapped mtime

[Yao Zi <ziyao@disroot.org>]

On Tue, Jul 29, 2025 at 04:25:14PM +0000, Uros Stajic wrote:
> The P8700 core does not support reading the time CSR directly and
> raises an illegal instruction exception. This patch adds support for
> reading the timer value via its memory-mapped address at 0x16108050
> when running on a P8700 processor.
> 
> Signed-off-by: Uros Stajic <uros.stajic@htecgroup.com>
> ---
>  drivers/timer/riscv_timer.c | 7 +++++++
>  1 file changed, 7 insertions(+)

Sorry that I didn't review v2 further, but

> diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
> index 1f4980ceb38..5138236a028 100644
> --- a/drivers/timer/riscv_timer.c
> +++ b/drivers/timer/riscv_timer.c
> @@ -18,8 +18,15 @@
>  #include <timer.h>
>  #include <asm/csr.h>
>  
> +#define P8700_TIMER_ADDR 0x16108050
> +
>  static u64 notrace riscv_timer_get_count(struct udevice *dev)
>  {
> +	if (IS_ENABLED(CONFIG_P8700_RISCV)) {
> +		u32 *mtime_addr = (u32 *)P8700_TIMER_ADDR;
> +		return *mtime_addr;
> +	}
> +

This introduces platform-specific code to the generic RISC-V
TIME-CSR-based timer driver.

If your platform doesn't implement a TIME CSR in hardware, I suggest
using riscv_aclint_timer.c if the provider of P8700_TIMER is
compatible with the RISC-V ACLINT specification, or just introducing a
new driver otherwise.

Regards,
Yao Zi

>  	__maybe_unused u32 hi, lo;
>  
>  	if (IS_ENABLED(CONFIG_64BIT))
> -- 
> 2.34.1