From: Leo Liang <ycliang@andestech.com>
To: <trini@konsulko.com>
Cc: <u-boot@lists.denx.de>, <ycliang@andestech.com>,
<rick@andestech.com>, <heinrich.schuchardt@canonical.com>,
<ben.dooks@codethink.co.uk>, <jamie.gibbons@microchip.com>,
<sputnik@on-the-web.ch>, <michal.simek@amd.com>
Subject: [GIT PULL] u-boot-riscv/master
Date: Tue, 12 Aug 2025 16:04:49 +0800 [thread overview]
Message-ID: <aJr1oclCSUMcK3bb@swlinux02> (raw)
Hi Tom,
The following changes since commit acfacf452441d0a659e3afbd55fd6061aa17e647:
Prepare v2025.10-rc2 (2025-08-11 13:47:46 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to bddcd6bcba081aaaaafe30d1b8f9f3c83f069bde:
starfive: fix return code of `mac write_eeprom` (2025-08-12 15:34:39 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27348
----------------------------------------------------------------
- Board: mbv: Prepare MBV for CI
- Board: MPFS Icicle Kit cleanup
- Board: Add Andes Voyager board support
- RISCV: Update SYS_BOOTM_LEN to commonly used value
- starfive: fix return code of `mac write_eeprom`
----------------------------------------------------------------
Heinrich Schuchardt (1):
starfive: fix return code of `mac write_eeprom`
Jamie Gibbons (6):
configs: microchip_mpfs_icicle: enable CONFIG_OF_BOARD_SETUP
board: microchip: mpfs_icicle: make use of ft_board_setup()
mailbox: add PolarFire SoC mailbox driver
misc: add PolarFire SoC system controller
board: microchip: mpfs_icicle: enable new driver configs
board: microchip: mpfs_icicle: update to use system controller
Leo Yu-Chi Liang (6):
riscv: board: Add Andes Voyager board Kconfig support
riscv: dts: andes: Add Voyager device tree
board: MAINTAINERS: Add Voyager board maintainer
board: andestech: Add Voyager board support
configs: andes: add Voyager board defconfig
doc: board: voyager: Add documentation for Voyager
Martin Herren (4):
riscv: Set SYS_BOOTM_LEN explicitly to 0x800000
riscv: Set SYS_BOOTM_LEN default to 0x4000000
riscv: Remove default SYS_BOOTM_LEN from defconfig
riscv: Increase Microchip Icicle's SYS_BOOTM_LEN
Michal Simek (4):
xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
xilinx: mbv: Add missing mmu-type cpu property
xilinx: mbv: Fix dt properties in interrupt controller node
xilinx: mbv: Use separate DTB for binman nodes
arch/riscv/Kconfig | 4 +
arch/riscv/dts/Makefile | 2 +
arch/riscv/dts/qilai-voyager.dts | 227 +++++++++++++++++++++
arch/riscv/dts/voyager-u-boot.dtsi | 52 +++++
arch/riscv/dts/xilinx-binman.dts | 12 ++
arch/riscv/dts/xilinx-mbv32.dts | 8 +-
arch/riscv/dts/xilinx-mbv64.dts | 8 +-
board/andestech/voyager/Kconfig | 44 ++++
board/andestech/voyager/MAINTAINERS | 7 +
board/andestech/voyager/Makefile | 6 +
board/andestech/voyager/voyager.c | 71 +++++++
board/microchip/mpfs_icicle/Kconfig | 4 +
board/microchip/mpfs_icicle/mpfs_icicle.c | 121 ++++++-----
.../starfive/visionfive2/visionfive2-i2c-eeprom.c | 8 +-
board/xilinx/mbv/Kconfig | 1 -
boot/Kconfig | 2 +-
configs/ae350_rv32_defconfig | 1 -
configs/ae350_rv32_falcon_defconfig | 1 -
configs/ae350_rv32_falcon_xip_defconfig | 1 -
configs/ae350_rv32_spl_defconfig | 1 -
configs/ae350_rv32_spl_xip_defconfig | 1 -
configs/ae350_rv32_xip_defconfig | 1 -
configs/ae350_rv64_defconfig | 1 -
configs/ae350_rv64_falcon_defconfig | 1 -
configs/ae350_rv64_falcon_xip_defconfig | 1 -
configs/ae350_rv64_spl_defconfig | 1 -
configs/ae350_rv64_spl_xip_defconfig | 1 -
configs/ae350_rv64_xip_defconfig | 1 -
configs/ibex-ast2700_defconfig | 1 -
configs/k230_canmv_defconfig | 1 +
configs/microchip_mpfs_icicle_defconfig | 4 +
configs/milkv_duo_defconfig | 1 -
configs/qemu-riscv32_defconfig | 1 -
configs/qemu-riscv32_smode_defconfig | 1 -
configs/qemu-riscv32_spl_defconfig | 1 -
configs/qemu-riscv64_defconfig | 1 -
configs/qemu-riscv64_smode_defconfig | 1 -
configs/qemu-riscv64_spl_defconfig | 1 -
configs/sifive_unleashed_defconfig | 1 -
configs/sifive_unmatched_defconfig | 1 -
configs/sipeed_licheerv_nano_defconfig | 1 -
configs/sipeed_maix_bitm_defconfig | 1 +
configs/sipeed_maix_smode_defconfig | 1 +
configs/starfive_visionfive2_defconfig | 1 -
configs/th1520_lpi4a_defconfig | 1 -
configs/voyager_spl_defconfig | 66 ++++++
configs/xilinx_mbv32_defconfig | 2 +
configs/xilinx_mbv32_smode_defconfig | 2 +
configs/xilinx_mbv64_defconfig | 2 +
configs/xilinx_mbv64_smode_defconfig | 2 +
doc/board/andestech/index.rst | 1 +
doc/board/andestech/voyager.rst | 81 ++++++++
drivers/mailbox/Kconfig | 7 +
drivers/mailbox/Makefile | 1 +
drivers/mailbox/mpfs-mbox.c | 177 ++++++++++++++++
drivers/misc/Kconfig | 9 +
drivers/misc/Makefile | 1 +
drivers/misc/mpfs_syscontroller.c | 157 ++++++++++++++
include/configs/voyager.h | 40 ++++
include/mpfs-mailbox.h | 67 ++++++
60 files changed, 1121 insertions(+), 103 deletions(-)
create mode 100644 arch/riscv/dts/qilai-voyager.dts
create mode 100644 arch/riscv/dts/voyager-u-boot.dtsi
create mode 100644 arch/riscv/dts/xilinx-binman.dts
create mode 100644 board/andestech/voyager/Kconfig
create mode 100644 board/andestech/voyager/MAINTAINERS
create mode 100644 board/andestech/voyager/Makefile
create mode 100644 board/andestech/voyager/voyager.c
create mode 100644 configs/voyager_spl_defconfig
create mode 100644 doc/board/andestech/voyager.rst
create mode 100644 drivers/mailbox/mpfs-mbox.c
create mode 100644 drivers/misc/mpfs_syscontroller.c
create mode 100644 include/configs/voyager.h
create mode 100644 include/mpfs-mailbox.h
Best regards,
Leo
next reply other threads:[~2025-08-12 8:05 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 8:04 Leo Liang [this message]
2025-08-12 15:22 ` [GIT PULL] u-boot-riscv/master Tom Rini
2025-08-13 6:57 ` Leo Liang
2025-08-13 11:16 ` Martin Herren
2025-08-13 11:59 ` Leo Liang
-- strict thread matches above, loose matches on Subject: below --
2025-10-16 12:07 [GIT,PULL] u-boot-riscv/master Leo Liang
2025-10-16 17:38 ` Tom Rini
2025-05-21 9:50 [GIT PULL] u-boot-riscv/master Leo Liang
2025-05-21 18:39 ` Tom Rini
2025-05-22 11:28 ` Conor Dooley
2025-05-22 14:45 ` Tom Rini
2025-05-22 15:36 ` Leo Liang
2025-05-22 15:54 ` Tom Rini
2025-05-22 16:40 ` Yao Zi
2025-05-23 9:18 ` Conor Dooley
2025-05-26 3:32 ` Mayuresh Chitale
2025-05-26 9:17 ` Conor Dooley
2025-05-26 14:56 ` Tom Rini
2025-05-26 17:34 ` Mayuresh Chitale
2025-05-26 18:16 ` Tom Rini
2025-05-27 17:10 ` Mayuresh Chitale
2025-05-27 17:34 ` Tom Rini
2025-04-25 10:07 Leo Liang
2025-04-25 10:35 ` Yao Zi
2025-04-26 14:14 ` Tom Rini
2025-04-25 12:57 ` E Shattow
2025-04-25 13:02 ` E Shattow
2025-04-25 23:43 ` Tom Rini
2025-04-26 1:13 ` E Shattow
2025-04-26 14:14 ` Tom Rini
2025-04-27 7:47 ` E Shattow
2025-03-25 6:19 Leo Liang
2025-03-25 20:18 ` Tom Rini
2025-03-06 12:18 Leo Liang
2025-03-07 11:20 ` Yao Zi
2025-02-20 5:13 Leo Liang
2025-02-20 17:19 ` Tom Rini
2025-02-03 8:17 Leo Liang
2025-02-03 21:26 ` Tom Rini
2025-01-17 1:53 Leo Liang
2025-01-17 17:56 ` Tom Rini
2024-11-27 13:08 Leo Liang
2024-11-27 18:54 ` Tom Rini
2024-11-06 12:12 Leo Liang
2024-11-08 16:51 ` Tom Rini
2024-11-11 13:24 ` Tom Rini
2024-10-29 12:33 Leo Liang
2024-10-29 16:37 ` Tom Rini
2024-10-28 12:24 Leo Liang
2024-10-28 19:33 ` Tom Rini
2024-07-22 8:29 Leo Liang
2024-07-22 19:31 ` Tom Rini
2024-05-30 8:56 Leo Liang
2024-06-03 17:42 ` Tom Rini
2024-05-14 13:28 Leo Liang
2024-05-14 16:14 ` Tom Rini
2024-05-01 16:38 Leo Liang
2024-05-02 14:42 ` Tom Rini
2024-04-09 8:25 Leo Liang
2024-04-10 0:43 ` Tom Rini
2024-03-26 13:22 Leo Liang
2024-03-27 12:12 ` Tom Rini
2024-03-12 8:51 Leo Liang
2024-03-12 18:52 ` Tom Rini
2024-01-31 10:21 Leo Liang
2024-01-31 14:14 ` Tom Rini
2023-12-14 2:38 Leo Yu-Chi Liang(梁育齊)
2023-12-14 12:19 ` Tom Rini
2023-12-14 12:46 ` Leo Liang
2023-12-14 14:39 ` Tom Rini
2023-12-07 13:46 Leo Liang
2023-12-09 20:59 ` Tom Rini
2023-11-02 10:49 Leo Liang
2023-11-02 14:53 ` Tom Rini
2021-02-26 1:53 Leo Liang
2021-02-26 17:40 ` Tom Rini
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