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From: Leo Liang <ycliang@andestech.com>
To: <Jamie.Gibbons@microchip.com>
Cc: <ziyao@disroot.org>, <u-boot@lists.denx.de>, <trini@konsulko.com>,
	<Conor.Dooley@microchip.com>,
	<Valentina.FernandezAlanis@microchip.com>,
	<junhui.liu@pigmoral.tech>, <rick@andestech.com>
Subject: Re: [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC
Date: Tue, 9 Dec 2025 11:17:38 +0800	[thread overview]
Message-ID: <aTeU0rLz6qDwpOdM@swlinux02> (raw)
In-Reply-To: <471395da081e977a4db8795e7cfd5022ebd058e6.camel@microchip.com>

Hi Jamie,

On Mon, Dec 08, 2025 at 12:10:28PM +0000, Jamie.Gibbons@microchip.com wrote:
> [EXTERNAL MAIL]
> 
> Hi Leo,
> 
> On Thu, 2025-12-04 at 15:45 +0800, Leo Liang wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> > the content is safe
> >
> > Hi Jamie,
> >
> > On Wed, Nov 19, 2025 at 12:38:42PM +0000, Jamie Gibbons wrote:
> > > [EXTERNAL MAIL]
> > >
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > >
> > > PolarFire SoC needs a custom implementation of top_of_ram(), so stop
> > > using the generic CPU & create a custom CPU instead.
> > >
> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > ---
> > >  arch/riscv/Kconfig                     |  1 +
> > >  arch/riscv/cpu/mpfs/Kconfig            | 16 +++++++++++
> > >  arch/riscv/cpu/mpfs/Makefile           |  6 ++++
> > >  arch/riscv/cpu/mpfs/cpu.c              | 22 +++++++++++++++
> > >  arch/riscv/cpu/mpfs/dram.c             | 38
> > > ++++++++++++++++++++++++++
> > >  arch/riscv/include/asm/arch-mpfs/clk.h |  8 ++++++
> > >  board/microchip/mpfs_generic/Kconfig   |  4 +--
> > >  7 files changed, 93 insertions(+), 2 deletions(-)
> > >  create mode 100644 arch/riscv/cpu/mpfs/Kconfig
> > >  create mode 100644 arch/riscv/cpu/mpfs/Makefile
> > >  create mode 100644 arch/riscv/cpu/mpfs/cpu.c
> >
> > The cpu.c file only contains "cleanup_before_linux" and seems
> > identical
> > with the one provided in arch/riscv/cpu/generic/cpu.c.
> >
> > Other than that, LGTM.
> >
> > If you don't mind, I could fix this on my side that you don't need to
> > resend the patchset again.
> >
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> 
> Thank you for your response, review and feedback.
> 
> Regarding 'mpfs/cpu.c', you're corect that it is currently identical to
> the generic implementation. Our intent was to provide a placeholder for
> any future Polarfire-specific logic and also assumed it was manditory,
> but if duplication is unneccessary, I'm happy for you to adjust as you
> see fit.
> 
> In other words, if U-Boot prefers to avoid duplication and this file is
> not mandatory for build or architextural reasons per CPU implementation,
> than please go ahead and use the generic version.

Got it! Thanks for the explanation.
I’ve updated it to use the generic implementation.
If any Polarfire-specific logic is needed in the future,
we can add this file back at that time.

Best regards,
Leo

> 
> Thanks,
> Jamie.
> 

  reply	other threads:[~2025-12-09  3:40 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-19 12:38 [PATCH 0/2] Add MPFS CPU Implementation Jamie Gibbons
2025-11-19 12:38 ` [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC Jamie Gibbons
2025-12-04  7:45   ` Leo Liang
2025-12-08 12:10     ` Jamie.Gibbons
2025-12-09  3:17       ` Leo Liang [this message]
2025-11-19 12:38 ` [PATCH 2/2] riscv: mpfs: move SoC level options to the CPU Kconfig Jamie Gibbons

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