[PATCH v1 0/3] Enable USB High-Speed support for QCS615

[PATCH v1 0/3] Enable USB High-Speed support for QCS615

[Balaji Selvanathan]

This series enables USB High-Speed functionality on QCS615 by
fixing clock configuration and adding QUSB2 PHY support.

Balaji Selvanathan (3):
  arm: dts: qcs615-ride: Remove unsupported USB clock reference
  clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support
  phy: qcom: qusb2: Add QCS615 QUSB2 PHY support

 arch/arm/dts/qcs615-ride-u-boot.dtsi | 14 ++++++++++
 drivers/clk/qcom/clock-qcs615.c      |  1 +
 drivers/phy/qcom/phy-qcom-qusb2.c    | 38 ++++++++++++++++++++++++++++
 3 files changed, 53 insertions(+)

-- 
2.34.1

[PATCH v1 1/3] arm: dts: qcs615-ride: Remove unsupported USB clock reference

[Balaji Selvanathan]

Remove GCC_USB3_PRIM_CLKREF_CLK from the USB controller node as it is
not implemented in the U-Boot clock driver. Keep only the supported
clocks to avoid clock warnings during boot.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 arch/arm/dts/qcs615-ride-u-boot.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi
index 68fffc70fcb..d8af124cc27 100644
--- a/arch/arm/dts/qcs615-ride-u-boot.dtsi
+++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi
@@ -11,4 +11,18 @@
 		      <0x0 0xc0000000 0x0 0xc0000000>,
 		      <0x1 0x80000000 0x1 0x00000000>;
 	};
+	soc@0 {
+		/* Remove GCC_USB3_PRIM_CLKREF_CLK from usb_1 node to avoid U-Boot clock warnings */
+		usb_1: usb@a6f8800 {
+			/delete-property/ clocks;
+			/delete-property/ clock-names;
+			/* Keep only the clocks that are implemented in U-Boot clock driver */
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+		};
+	};
 };
-- 
2.34.1

[PATCH v1 2/3] clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support

[Balaji Selvanathan]

Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/clk/qcom/clock-qcs615.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
index 4700baba8c9..2b59c4d13fd 100644
--- a/drivers/clk/qcom/clock-qcs615.c
+++ b/drivers/clk/qcom/clock-qcs615.c
@@ -66,6 +66,7 @@ static const struct gate_clk qcs615_clks[] = {
 	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
 	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
 	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
+	GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)),
 	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
-- 
2.34.1

[PATCH v1 3/3] phy: qcom: qusb2: Add QCS615 QUSB2 PHY support

[Balaji Selvanathan]

Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.

This change is based on the upstream Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/qualcomm/phy-qcom-qusb2.c?id=3d25d46a255a83f94d7d4d4216f38aafc8e116b0

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/phy/qcom/phy-qcom-qusb2.c | 38 +++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
index d98f6108e69..a5d724eebd4 100644
--- a/drivers/phy/qcom/phy-qcom-qusb2.c
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = {
 	[QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
 };
 
+static const unsigned int ipq6018_regs_layout[] = {
+	[QUSB2PHY_PLL_STATUS] = 0x38,
+	[QUSB2PHY_PORT_TUNE1] = 0x80,
+	[QUSB2PHY_PORT_TUNE2] = 0x84,
+	[QUSB2PHY_PORT_TUNE3] = 0x88,
+	[QUSB2PHY_PORT_TUNE4] = 0x8C,
+	[QUSB2PHY_PORT_TUNE5] = 0x90,
+	[QUSB2PHY_PORT_TEST1] = 0x98,
+	[QUSB2PHY_PORT_TEST2] = 0x9C,
+	[QUSB2PHY_PORT_POWERDOWN] = 0xB4,
+	[QUSB2PHY_INTR_CTRL] = 0xBC,
+};
+
 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
 	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
 	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
@@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
 	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 };
 
+static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
+	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8),
+	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
+	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
+	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
+	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
+	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
+	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
+	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
+	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
+	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
+};
+
 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
 	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
 	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
@@ -248,6 +274,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
 	.autoresume_en = BIT(3),
 };
 
+static const struct qusb2_phy_cfg qcs615_phy_cfg = {
+	.tbl = qcs615_init_tbl,
+	.tbl_num = ARRAY_SIZE(qcs615_init_tbl),
+	.regs = ipq6018_regs_layout,
+
+	.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
+	.mask_core_ready = PLL_LOCKED,
+	.autoresume_en = BIT(0),
+};
+
 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
 	.tbl = qusb2_v2_init_tbl,
 	.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
@@ -453,6 +489,8 @@ static const struct udevice_id qusb2phy_ids[] = {
 	{ .compatible = "qcom,qusb2-phy" },
 	{ .compatible = "qcom,qcm2290-qusb2-phy",
 	  .data = (ulong)&sm6115_phy_cfg },
+	{ .compatible = "qcom,qcs615-qusb2-phy",
+	  .data = (ulong)&qcs615_phy_cfg },
 	{ .compatible = "qcom,sdm660-qusb2-phy",
 	  .data = (ulong)&sdm660_phy_cfg },
 	{ .compatible = "qcom,sm6115-qusb2-phy",
-- 
2.34.1

Re: [PATCH v1 2/3] clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support

[neil.armstrong]

On 11/14/25 07:38, Balaji Selvanathan wrote:
> Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
> clock driver. This clock is required for proper PHY operation
> and eliminates clock-related warnings during USB initialization.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   drivers/clk/qcom/clock-qcs615.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
> index 4700baba8c9..2b59c4d13fd 100644
> --- a/drivers/clk/qcom/clock-qcs615.c
> +++ b/drivers/clk/qcom/clock-qcs615.c
> @@ -66,6 +66,7 @@ static const struct gate_clk qcs615_clks[] = {
>   	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
>   	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
>   	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
> +	GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)),
>   	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
>   	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
>   	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v1 3/3] phy: qcom: qusb2: Add QCS615 QUSB2 PHY support

[neil.armstrong]

On 11/14/25 07:38, Balaji Selvanathan wrote:
> Add support for QCS615 QUSB2 PHY by introducing platform-specific
> initialization table and register layout. The implementation reuses
> the IPQ6018 register layout and defines QCS615-specific tuning
> parameters for proper USB PHY operation.
> 
> This change is based on the upstream Linux kernel implementation:
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/qualcomm/phy-qcom-qusb2.c?id=3d25d46a255a83f94d7d4d4216f38aafc8e116b0
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   drivers/phy/qcom/phy-qcom-qusb2.c | 38 +++++++++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
> index d98f6108e69..a5d724eebd4 100644
> --- a/drivers/phy/qcom/phy-qcom-qusb2.c
> +++ b/drivers/phy/qcom/phy-qcom-qusb2.c
> @@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = {
>   	[QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
>   };
>   
> +static const unsigned int ipq6018_regs_layout[] = {
> +	[QUSB2PHY_PLL_STATUS] = 0x38,
> +	[QUSB2PHY_PORT_TUNE1] = 0x80,
> +	[QUSB2PHY_PORT_TUNE2] = 0x84,
> +	[QUSB2PHY_PORT_TUNE3] = 0x88,
> +	[QUSB2PHY_PORT_TUNE4] = 0x8C,
> +	[QUSB2PHY_PORT_TUNE5] = 0x90,
> +	[QUSB2PHY_PORT_TEST1] = 0x98,
> +	[QUSB2PHY_PORT_TEST2] = 0x9C,
> +	[QUSB2PHY_PORT_POWERDOWN] = 0xB4,
> +	[QUSB2PHY_INTR_CTRL] = 0xBC,
> +};
> +
>   static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
>   	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
>   	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
> @@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
>   	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
>   };
>   
> +static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
> +};
> +
>   static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
>   	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
>   	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
> @@ -248,6 +274,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
>   	.autoresume_en = BIT(3),
>   };
>   
> +static const struct qusb2_phy_cfg qcs615_phy_cfg = {
> +	.tbl = qcs615_init_tbl,
> +	.tbl_num = ARRAY_SIZE(qcs615_init_tbl),
> +	.regs = ipq6018_regs_layout,
> +
> +	.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> +	.mask_core_ready = PLL_LOCKED,
> +	.autoresume_en = BIT(0),
> +};
> +
>   static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>   	.tbl = qusb2_v2_init_tbl,
>   	.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
> @@ -453,6 +489,8 @@ static const struct udevice_id qusb2phy_ids[] = {
>   	{ .compatible = "qcom,qusb2-phy" },
>   	{ .compatible = "qcom,qcm2290-qusb2-phy",
>   	  .data = (ulong)&sm6115_phy_cfg },
> +	{ .compatible = "qcom,qcs615-qusb2-phy",
> +	  .data = (ulong)&qcs615_phy_cfg },
>   	{ .compatible = "qcom,sdm660-qusb2-phy",
>   	  .data = (ulong)&sdm660_phy_cfg },
>   	{ .compatible = "qcom,sm6115-qusb2-phy",

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH v1 1/3] arm: dts: qcs615-ride: Remove unsupported USB clock reference

[Sumit Garg]

On Fri, Nov 14, 2025 at 12:08:02PM +0530, Balaji Selvanathan wrote:
> Remove GCC_USB3_PRIM_CLKREF_CLK from the USB controller node as it is
> not implemented in the U-Boot clock driver. Keep only the supported
> clocks to avoid clock warnings during boot.

Rather than overriding DT, why can't this be implmented in U-Boot? And
how why it isn't an essential clock for U-Boot operation?

-Sumit

> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  arch/arm/dts/qcs615-ride-u-boot.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi
> index 68fffc70fcb..d8af124cc27 100644
> --- a/arch/arm/dts/qcs615-ride-u-boot.dtsi
> +++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi
> @@ -11,4 +11,18 @@
>  		      <0x0 0xc0000000 0x0 0xc0000000>,
>  		      <0x1 0x80000000 0x1 0x00000000>;
>  	};
> +	soc@0 {
> +		/* Remove GCC_USB3_PRIM_CLKREF_CLK from usb_1 node to avoid U-Boot clock warnings */
> +		usb_1: usb@a6f8800 {
> +			/delete-property/ clocks;
> +			/delete-property/ clock-names;
> +			/* Keep only the clocks that are implemented in U-Boot clock driver */
> +			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> +				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> +				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> +				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> +				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
> +			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
> +		};
> +	};
>  };
> -- 
> 2.34.1
> 

Re: [PATCH v1 3/3] phy: qcom: qusb2: Add QCS615 QUSB2 PHY support

[Sumit Garg]

On Fri, Nov 14, 2025 at 12:08:04PM +0530, Balaji Selvanathan wrote:
> Add support for QCS615 QUSB2 PHY by introducing platform-specific
> initialization table and register layout. The implementation reuses
> the IPQ6018 register layout and defines QCS615-specific tuning
> parameters for proper USB PHY operation.
> 
> This change is based on the upstream Linux kernel implementation:
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/qualcomm/phy-qcom-qusb2.c?id=3d25d46a255a83f94d7d4d4216f38aafc8e116b0
>

This kernel reference doesn't contain qcs615 specific implementation.
Once you update that, feel free to add:

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/phy/qcom/phy-qcom-qusb2.c | 38 +++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
> index d98f6108e69..a5d724eebd4 100644
> --- a/drivers/phy/qcom/phy-qcom-qusb2.c
> +++ b/drivers/phy/qcom/phy-qcom-qusb2.c
> @@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = {
>  	[QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
>  };
>  
> +static const unsigned int ipq6018_regs_layout[] = {
> +	[QUSB2PHY_PLL_STATUS] = 0x38,
> +	[QUSB2PHY_PORT_TUNE1] = 0x80,
> +	[QUSB2PHY_PORT_TUNE2] = 0x84,
> +	[QUSB2PHY_PORT_TUNE3] = 0x88,
> +	[QUSB2PHY_PORT_TUNE4] = 0x8C,
> +	[QUSB2PHY_PORT_TUNE5] = 0x90,
> +	[QUSB2PHY_PORT_TEST1] = 0x98,
> +	[QUSB2PHY_PORT_TEST2] = 0x9C,
> +	[QUSB2PHY_PORT_POWERDOWN] = 0xB4,
> +	[QUSB2PHY_INTR_CTRL] = 0xBC,
> +};
> +
>  static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
>  	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
>  	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
> @@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
>  };
>  
> +static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
> +};
> +
>  static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
> @@ -248,6 +274,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
>  	.autoresume_en = BIT(3),
>  };
>  
> +static const struct qusb2_phy_cfg qcs615_phy_cfg = {
> +	.tbl = qcs615_init_tbl,
> +	.tbl_num = ARRAY_SIZE(qcs615_init_tbl),
> +	.regs = ipq6018_regs_layout,
> +
> +	.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> +	.mask_core_ready = PLL_LOCKED,
> +	.autoresume_en = BIT(0),
> +};
> +
>  static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>  	.tbl = qusb2_v2_init_tbl,
>  	.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
> @@ -453,6 +489,8 @@ static const struct udevice_id qusb2phy_ids[] = {
>  	{ .compatible = "qcom,qusb2-phy" },
>  	{ .compatible = "qcom,qcm2290-qusb2-phy",
>  	  .data = (ulong)&sm6115_phy_cfg },
> +	{ .compatible = "qcom,qcs615-qusb2-phy",
> +	  .data = (ulong)&qcs615_phy_cfg },
>  	{ .compatible = "qcom,sdm660-qusb2-phy",
>  	  .data = (ulong)&sdm660_phy_cfg },
>  	{ .compatible = "qcom,sm6115-qusb2-phy",
> -- 
> 2.34.1
> 

Re: [PATCH v1 2/3] clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support

[Sumit Garg]

On Fri, Nov 14, 2025 at 12:08:03PM +0530, Balaji Selvanathan wrote:
> Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
> clock driver. This clock is required for proper PHY operation
> and eliminates clock-related warnings during USB initialization.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/clock-qcs615.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> 
> diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
> index 4700baba8c9..2b59c4d13fd 100644
> --- a/drivers/clk/qcom/clock-qcs615.c
> +++ b/drivers/clk/qcom/clock-qcs615.c
> @@ -66,6 +66,7 @@ static const struct gate_clk qcs615_clks[] = {
>  	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
> +	GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
> -- 
> 2.34.1
> 

Re: [PATCH v1 1/3] arm: dts: qcs615-ride: Remove unsupported USB clock reference

[Balaji Selvanathan]

Hi Sumit,

Thanks for the feedback. Please find reply below.

On 12/26/2025 3:52 PM, Sumit Garg wrote:
> On Fri, Nov 14, 2025 at 12:08:02PM +0530, Balaji Selvanathan wrote:
>> Remove GCC_USB3_PRIM_CLKREF_CLK from the USB controller node as it is
>> not implemented in the U-Boot clock driver. Keep only the supported
>> clocks to avoid clock warnings during boot.
> Rather than overriding DT, why can't this be implmented in U-Boot? And
> how why it isn't an essential clock for U-Boot operation?
>
> -Sumit

GCC_USB3_PRIM_CLKREF_CLK seems to be a reference clock that is enabled 
by earlier boot stages before U-Boot starts: The clock is already ON 
when U-Boot starts - verified during boot. This is a reference clock 
with hardware voting mechanism, not typically controlled by software.

Without this override, we get "Clock 152 not found" warning message (as 
it is not there in the QCS615 clock driver.

Regards,

Balaji


>
>> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>> ---
>>   arch/arm/dts/qcs615-ride-u-boot.dtsi | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi
>> index 68fffc70fcb..d8af124cc27 100644
>> --- a/arch/arm/dts/qcs615-ride-u-boot.dtsi
>> +++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi
>> @@ -11,4 +11,18 @@
>>   		      <0x0 0xc0000000 0x0 0xc0000000>,
>>   		      <0x1 0x80000000 0x1 0x00000000>;
>>   	};
>> +	soc@0 {
>> +		/* Remove GCC_USB3_PRIM_CLKREF_CLK from usb_1 node to avoid U-Boot clock warnings */
>> +		usb_1: usb@a6f8800 {
>> +			/delete-property/ clocks;
>> +			/delete-property/ clock-names;
>> +			/* Keep only the clocks that are implemented in U-Boot clock driver */
>> +			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
>> +				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
>> +				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
>> +				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
>> +				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
>> +			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
>> +		};
>> +	};
>>   };
>> -- 
>> 2.34.1
>>

Re: [PATCH v1 1/3] arm: dts: qcs615-ride: Remove unsupported USB clock reference

[Sumit Garg]

On Tue, Jan 20, 2026 at 10:00:58AM +0530, Balaji Selvanathan wrote:
> Hi Sumit,
> 
> Thanks for the feedback. Please find reply below.
> 
> On 12/26/2025 3:52 PM, Sumit Garg wrote:
> > On Fri, Nov 14, 2025 at 12:08:02PM +0530, Balaji Selvanathan wrote:
> > > Remove GCC_USB3_PRIM_CLKREF_CLK from the USB controller node as it is
> > > not implemented in the U-Boot clock driver. Keep only the supported
> > > clocks to avoid clock warnings during boot.
> > Rather than overriding DT, why can't this be implmented in U-Boot? And
> > how why it isn't an essential clock for U-Boot operation?
> > 
> > -Sumit
> 
> GCC_USB3_PRIM_CLKREF_CLK seems to be a reference clock that is enabled by
> earlier boot stages before U-Boot starts: The clock is already ON when
> U-Boot starts - verified during boot. This is a reference clock with
> hardware voting mechanism, not typically controlled by software.
> 
> Without this override, we get "Clock 152 not found" warning message (as it
> is not there in the QCS615 clock driver.

Why not implement this clock handling in the U-Boot as it is being
handled in the kernel (see: drivers/clk/qcom/gcc-qcs615.c +2886)? You
can also seek a reference from sdm845, qcm2290 clk drivers in U-Boot
too.

Using DT overrides for missing simple functionality in U-Boot isn't
acceptable since we want to avoid as much overrides as possible.

-Sumit

> 
> Regards,
> 
> Balaji
> 
> 
> > 
> > > Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> > > ---
> > >   arch/arm/dts/qcs615-ride-u-boot.dtsi | 14 ++++++++++++++
> > >   1 file changed, 14 insertions(+)
> > > 
> > > diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi
> > > index 68fffc70fcb..d8af124cc27 100644
> > > --- a/arch/arm/dts/qcs615-ride-u-boot.dtsi
> > > +++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi
> > > @@ -11,4 +11,18 @@
> > >   		      <0x0 0xc0000000 0x0 0xc0000000>,
> > >   		      <0x1 0x80000000 0x1 0x00000000>;
> > >   	};
> > > +	soc@0 {
> > > +		/* Remove GCC_USB3_PRIM_CLKREF_CLK from usb_1 node to avoid U-Boot clock warnings */
> > > +		usb_1: usb@a6f8800 {
> > > +			/delete-property/ clocks;
> > > +			/delete-property/ clock-names;
> > > +			/* Keep only the clocks that are implemented in U-Boot clock driver */
> > > +			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> > > +				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> > > +				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> > > +				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> > > +				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
> > > +			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
> > > +		};
> > > +	};
> > >   };
> > > -- 
> > > 2.34.1
> > >