Re: [RESEND v2 2/6] phy: Add IPQ9574 support to Qualcomm QUSB2 phy

[Sumit Garg <sumit.garg@kernel.org>]

On Thu, Dec 18, 2025 at 11:45:53AM +0530, Varadarajan Narayanan wrote:
> Imported from Linux driver.

Kindly add information as to which kernel driver commit you have used to
import this code.

-Sumit

> 
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---
>  drivers/phy/qcom/phy-qcom-qusb2.c | 42 +++++++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
> index d98f6108e69..df82f2a99da 100644
> --- a/drivers/phy/qcom/phy-qcom-qusb2.c
> +++ b/drivers/phy/qcom/phy-qcom-qusb2.c
> @@ -152,6 +152,22 @@ enum qusb2phy_reg_layout {
>  		.offset = o, .val = v, .in_layout = 1, \
>  	}
>  
> +static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
> +};
> +
>  static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
>  	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
>  	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
> @@ -168,6 +184,19 @@ static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
>  };
>  
> +static const unsigned int ipq6018_regs_layout[] = {
> +	[QUSB2PHY_PLL_STATUS]		= 0x38,
> +	[QUSB2PHY_PORT_TUNE1]		= 0x80,
> +	[QUSB2PHY_PORT_TUNE2]		= 0x84,
> +	[QUSB2PHY_PORT_TUNE3]		= 0x88,
> +	[QUSB2PHY_PORT_TUNE4]		= 0x8C,
> +	[QUSB2PHY_PORT_TUNE5]		= 0x90,
> +	[QUSB2PHY_PORT_TEST1]		= 0x98,
> +	[QUSB2PHY_PORT_TEST2]		= 0x9C,
> +	[QUSB2PHY_PORT_POWERDOWN]	= 0xB4,
> +	[QUSB2PHY_INTR_CTRL]		= 0xBC,
> +};
> +
>  static const unsigned int sm6115_regs_layout[] = {
>  	[QUSB2PHY_PLL_STATUS] = 0x38,	  [QUSB2PHY_PORT_TUNE1] = 0x80,
>  	[QUSB2PHY_PORT_TUNE2] = 0x84,	  [QUSB2PHY_PORT_TUNE3] = 0x88,
> @@ -224,6 +253,17 @@ static const unsigned int qusb2_v2_regs_layout[] = {
>  	[QUSB2PHY_INTR_CTRL] = 0x230,
>  };
>  
> +static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
> +	.tbl            = ipq6018_init_tbl,
> +	.tbl_num        = ARRAY_SIZE(ipq6018_init_tbl),
> +	.regs           = ipq6018_regs_layout,
> +
> +	.disable_ctrl   = POWER_DOWN,
> +	.mask_core_ready = PLL_LOCKED,
> +	/* autoresume not used */
> +	.autoresume_en   = BIT(0),
> +};
> +
>  static const struct qusb2_phy_cfg sm6115_phy_cfg = {
>  	.tbl = sm6115_init_tbl,
>  	.tbl_num = ARRAY_SIZE(sm6115_init_tbl),
> @@ -455,6 +495,8 @@ static const struct udevice_id qusb2phy_ids[] = {
>  	  .data = (ulong)&sm6115_phy_cfg },
>  	{ .compatible = "qcom,sdm660-qusb2-phy",
>  	  .data = (ulong)&sdm660_phy_cfg },
> +	{ .compatible = "qcom,ipq9574-qusb2-phy",
> +	  .data = (ulong)&ipq6018_phy_cfg },
>  	{ .compatible = "qcom,sm6115-qusb2-phy",
>  	  .data = (ulong)&sm6115_phy_cfg },
>  	{ .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg },
> -- 
> 2.34.1
>