[PATCH 0/5] rockchip: sdram: allow reading memory info from TPL on non-ARM64

[PATCH 0/5] rockchip: sdram: allow reading memory info from TPL on non-ARM64

[Aaron Griffith]

The RK3506 TPL provides memory info to the bootloader via ATAGS. There
is already an implementation that reads this information on RK3588 and
others, but it is currently gated behind CONFIG_ARM64. The RK3506 is
*not* ARM64.

This patch series aims to allow this code to be used on non-ARM64, by

 * adding a new config option to read this info from the TPL,
 * allowing the ATAGS memory area it uses to be set in config headers,
 * placing truly ARM64-specific logic behind CONFIG_ARM64.

I'm working on upstreaming RK3506 support, and this is the first patch
series of hopefully many in that direction.

Signed-off-by: Aaron Griffith <aargri@gmail.com>
---
Aaron Griffith (5):
      rockchip: sdram: add option to read bank information from TPL
      rockchip: sdram: remove redundant configuration checks
      rockchip: sdram: allow config headers to override ATAGs location
      rockchip: sdram: refactor bi_dram logic into separate function
      rockchip: sdram: only reserve BL31 and use mem_map on ARM64

 arch/arm/mach-rockchip/Kconfig |  11 +++
 arch/arm/mach-rockchip/sdram.c | 195 ++++++++++++++++++++++-------------------
 2 files changed, 118 insertions(+), 88 deletions(-)
---
base-commit: 0f6ff53d55ba254de8a995c2a2f5a313acd40ac7
change-id: 20251226-rockchip-tpl-use-atags-bf3d14a840ca

Best regards,
-- 
Aaron Griffith <aargri@gmail.com>

[PATCH 1/5] rockchip: sdram: add option to read bank information from TPL

[Aaron Griffith]

Existing code to read DDR_MEM tags from the Rockchip external TPL is
gated behind CONFIG_ARM64. These changes instead place it behind a new
config, ROCKCHIP_EXTERNAL_TPL_DDR_MEM. This option is implied by the
four SoCs that currently use this feature (RK3528, RK3568, RK3576, and
RK3588).

Signed-off-by: Aaron Griffith <aargri@gmail.com>
---
 arch/arm/mach-rockchip/Kconfig | 11 +++++++++++
 arch/arm/mach-rockchip/sdram.c | 12 +++++++-----
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e32e49ff59acc633feba96f8870754b60fc366c6..1f80ff3136e2bb565a2f4be59d9b025dd0d70d95 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -348,6 +348,7 @@ config ROCKCHIP_RK3528
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SPL_ATF
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -392,6 +393,7 @@ config ROCKCHIP_RK3568
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
 	imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
@@ -432,6 +434,7 @@ config ROCKCHIP_RK3576
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SPL_ATF
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -477,6 +480,7 @@ config ROCKCHIP_RK3588
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SCMI_FIRMWARE
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -608,6 +612,13 @@ config ROCKCHIP_EXTERNAL_TPL
 	  Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
 	  include the external TPL in the image built by binman.
 
+config ROCKCHIP_EXTERNAL_TPL_DDR_MEM
+	bool "Use DDR_MEM information from external TPL"
+	depends on ROCKCHIP_EXTERNAL_TPL
+	help
+	  Some Rockchip external TPLs provide information about DDR memory.
+	  Enable this option to parse and use this information.
+
 config ROCKCHIP_BOOT_MODE_REG
 	hex "Rockchip boot mode flag register address"
 	help
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index d560f90e873d02e1a799ab0d7c1e085df0c1c54a..f549baaa8e7e0664029f37de012dd22dfe92b07f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -36,7 +36,7 @@ struct tos_parameter_t {
 	s64 reserve[8];
 };
 
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 /* Tag size and offset */
 #define ATAGS_SIZE		SZ_8K
 #define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
@@ -287,14 +287,14 @@ static int rockchip_dram_init_banksize(void)
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM */
 
 int dram_init_banksize(void)
 {
 	size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
 	size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
 
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	int ret = rockchip_dram_init_banksize();
 
 	if (!ret)
@@ -302,7 +302,9 @@ int dram_init_banksize(void)
 
 	debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
 	      ret);
+#endif
 
+#ifdef CONFIG_ARM64
 	/* Reserve 2M for ATF bl31 */
 	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
 	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
@@ -314,7 +316,7 @@ int dram_init_banksize(void)
 	} else if (ram_top > SZ_4G && top == SZ_4G) {
 		gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
 	}
-#else
+#else /* !CONFIG_ARM64 */
 #ifdef CONFIG_SPL_OPTEE_IMAGE
 	struct tos_parameter_t *tos_parameter;
 
@@ -340,7 +342,7 @@ int dram_init_banksize(void)
 	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
 #endif
-#endif
+#endif /* CONFIG_ARM64 */
 
 	return 0;
 }

-- 
2.47.3

[PATCH 2/5] rockchip: sdram: remove redundant configuration checks

[Aaron Griffith]

The new config option that enables this code guarantees
ROCKCHIP_EXTERNAL_TPL, and is implied by these four SoC configs,
making these checks redundant.

Signed-off-by: Aaron Griffith <aargri@gmail.com>
---
 arch/arm/mach-rockchip/sdram.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index f549baaa8e7e0664029f37de012dd22dfe92b07f..2f39928bcbda2936fb4f079bbb72fa13f80af6c0 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -109,15 +109,6 @@ static int rockchip_dram_init_banksize(void)
 	u32 calc_hash;
 	u8 i, j;
 
-	if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
-	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
-	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
-	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
-		return -ENOTSUPP;
-
-	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
-		return -ENOTSUPP;
-
 	/* Find DDR_MEM tag */
 	while (addr < (u32 *)ATAGS_PHYS_END) {
 		tag_h = (const struct tag_header *)addr;

-- 
2.47.3

[PATCH 3/5] rockchip: sdram: allow config headers to override ATAGs location

[Aaron Griffith]

The Rockchip TPL on some SoCs (notably RK3506) place the ATAGS region
somewhere other than the default this code expects. This change allows
that region to be placed somewhere different by defining ATAGS_SIZE
and ATAGS_OFFSET inside a configuration header for either the SoC or
the board.

Signed-off-by: Aaron Griffith <aargri@gmail.com>
---
 arch/arm/mach-rockchip/sdram.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 2f39928bcbda2936fb4f079bbb72fa13f80af6c0..98c02570dc4e4a8315c25a5caad5d568db10c5d8 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -38,8 +38,12 @@ struct tos_parameter_t {
 
 #ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 /* Tag size and offset */
+#ifndef ATAGS_SIZE
 #define ATAGS_SIZE		SZ_8K
+#endif
+#ifndef ATAGS_OFFSET
 #define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
+#endif
 #define ATAGS_PHYS_BASE		(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
 #define ATAGS_PHYS_END		(ATAGS_PHYS_BASE + ATAGS_SIZE)
 

-- 
2.47.3

[PATCH 4/5] rockchip: sdram: refactor bi_dram logic into separate function

[Aaron Griffith]

This part of rockchip_dram_init_banksize decides what to do with the
memory information it reads out of ATAGS. Right now, this is used to
add holes for reserved memory from mem_map and for BL31.

This change factors it out into a separate function. This function is
marked weak, so that a board or SoC can implement its own logic for
reserved memory. For example, the RK3506 has no BL31, and should not
reserve memory for it.

This new function body is a copy of the existing code with only two
small changes:

 * Replace index j with *next_bank in function body.

 * Increment *next_bank at the end of the function, rather than in the
   for-loop that calls this function. This makes the meaning of the
   *next_bank argument more consistent: it is always incremented when
   a bank is added.

Signed-off-by: Aaron Griffith <aargri@gmail.com>
---
 arch/arm/mach-rockchip/sdram.c | 234 ++++++++++++++++++++++-------------------
 1 file changed, 127 insertions(+), 107 deletions(-)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 98c02570dc4e4a8315c25a5caad5d568db10c5d8..287073c0e50839cc9366baacbc47512dbe2b4476 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -105,6 +105,129 @@ static u32 js_hash(const void *buf, u32 len)
 	return hash;
 }
 
+/*
+ * Populate gd->bd->bi_dram[*next_bank] (and possibly banks after) with
+ * the memory region received from the TPL starting at start_addr with
+ * given size.
+ *
+ * Increment *next_bank by the number of used banks.
+ */
+__weak int rockchip_dram_init_banksize_add_bank(u8 *next_bank, phys_addr_t start_addr,
+						phys_size_t size)
+{
+	struct mm_region *tmp_mem_map = mem_map;
+	phys_addr_t end_addr;
+
+	/*
+	 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
+	 * have it, so force this space as reserved.
+	 */
+	if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
+		size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
+		start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
+	}
+
+	/*
+	 * Put holes for reserved memory areas from mem_map.
+	 *
+	 * Only check for at most one overlap with one reserved memory
+	 * area.
+	 */
+	while (tmp_mem_map->size) {
+		const phys_addr_t rsrv_start = tmp_mem_map->phys;
+		const phys_size_t rsrv_size = tmp_mem_map->size;
+		const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
+
+		/*
+		 * DRAM memories are expected by Arm to be marked as
+		 * Normal Write-back cacheable, Inner shareable[1], so
+		 * let's filter on that to put holes in non-DRAM areas.
+		 *
+		 * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
+		 */
+		const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE;
+		/*
+		 * (AttrIndx | SH) in Lower Attributes of Block
+		 * Descriptor[2].
+		 * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+		 */
+		const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8);
+
+		if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
+			tmp_mem_map++;
+			continue;
+		}
+
+		/*
+		 * If the start of the DDR_MEM tag is in a reserved
+		 * memory area, move start address and resize.
+		 */
+		if (start_addr >= rsrv_start && start_addr < rsrv_end) {
+			if (rsrv_end - start_addr > size) {
+				debug("Would be negative memory size\n");
+				return -EINVAL;
+			}
+
+			size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
+			start_addr = rsrv_end;
+			break;
+		}
+
+		if (start_addr < rsrv_start) {
+			end_addr = start_addr + size;
+
+			if (end_addr <= rsrv_start) {
+				tmp_mem_map++;
+				continue;
+			}
+
+			/*
+			 * If the memory area overlaps a reserved memory
+			 * area with start address outside of reserved
+			 * memory area and...
+			 *
+			 * ... ends in the middle of reserved memory
+			 * area, resize.
+			 */
+			if (end_addr <= rsrv_end) {
+				size = rsrv_start - start_addr;
+				break;
+			}
+
+			/*
+			 * ... ends after the reserved memory area,
+			 * split the region in two, one for before the
+			 * reserved memory area and one for after.
+			 */
+			gd->bd->bi_dram[*next_bank].start = start_addr;
+			gd->bd->bi_dram[*next_bank].size = rsrv_start - start_addr;
+
+			*next_bank += 1;
+
+			size = end_addr - rsrv_end;
+			start_addr = rsrv_end;
+
+			break;
+		}
+
+		tmp_mem_map++;
+	}
+
+	if (*next_bank > CONFIG_NR_DRAM_BANKS) {
+		debug("Too many banks, max allowed (%d)\n",
+		      CONFIG_NR_DRAM_BANKS);
+		return -ENOMEM;
+	}
+
+	gd->bd->bi_dram[*next_bank].start = start_addr;
+	gd->bd->bi_dram[*next_bank].size = size;
+
+	*next_bank += 1;
+
+	return 0;
+}
+
 static int rockchip_dram_init_banksize(void)
 {
 	const struct tag_header *tag_h = NULL;
@@ -168,116 +291,13 @@ static int rockchip_dram_init_banksize(void)
 	 * Rockchip guaranteed DDR_MEM is ordered so no need to worry about
 	 * bi_dram order.
 	 */
-	for (i = 0, j = 0; i < ddr_info->count; i++, j++) {
+	for (i = 0, j = 0; i < ddr_info->count; i++) {
 		phys_size_t size = ddr_info->bank[(i + ddr_info->count)];
 		phys_addr_t start_addr = ddr_info->bank[i];
-		struct mm_region *tmp_mem_map = mem_map;
-		phys_addr_t end_addr;
-
-		/*
-		 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
-		 * have it, so force this space as reserved.
-		 */
-		if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
-			size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
-			start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
-		}
-
-		/*
-		 * Put holes for reserved memory areas from mem_map.
-		 *
-		 * Only check for at most one overlap with one reserved memory
-		 * area.
-		 */
-		while (tmp_mem_map->size) {
-			const phys_addr_t rsrv_start = tmp_mem_map->phys;
-			const phys_size_t rsrv_size = tmp_mem_map->size;
-			const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
-
-			/*
-			 * DRAM memories are expected by Arm to be marked as
-			 * Normal Write-back cacheable, Inner shareable[1], so
-			 * let's filter on that to put holes in non-DRAM areas.
-			 *
-			 * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
-			 */
-			const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-				PTE_BLOCK_INNER_SHARE;
-			/*
-			 * (AttrIndx | SH) in Lower Attributes of Block
-			 * Descriptor[2].
-			 * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
-			 */
-			const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8);
-
-			if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
-				tmp_mem_map++;
-				continue;
-			}
-
-			/*
-			 * If the start of the DDR_MEM tag is in a reserved
-			 * memory area, move start address and resize.
-			 */
-			if (start_addr >= rsrv_start && start_addr < rsrv_end) {
-				if (rsrv_end - start_addr > size) {
-					debug("Would be negative memory size\n");
-					return -EINVAL;
-				}
-
-				size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
-				start_addr = rsrv_end;
-				break;
-			}
-
-			if (start_addr < rsrv_start) {
-				end_addr = start_addr + size;
-
-				if (end_addr <= rsrv_start) {
-					tmp_mem_map++;
-					continue;
-				}
-
-				/*
-				 * If the memory area overlaps a reserved memory
-				 * area with start address outside of reserved
-				 * memory area and...
-				 *
-				 * ... ends in the middle of reserved memory
-				 * area, resize.
-				 */
-				if (end_addr <= rsrv_end) {
-					size = rsrv_start - start_addr;
-					break;
-				}
-
-				/*
-				 * ... ends after the reserved memory area,
-				 * split the region in two, one for before the
-				 * reserved memory area and one for after.
-				 */
-				gd->bd->bi_dram[j].start = start_addr;
-				gd->bd->bi_dram[j].size = rsrv_start - start_addr;
-
-				j++;
-
-				size = end_addr - rsrv_end;
-				start_addr = rsrv_end;
-
-				break;
-			}
-
-			tmp_mem_map++;
-		}
-
-		if (j > CONFIG_NR_DRAM_BANKS) {
-			debug("Too many banks, max allowed (%d)\n",
-			      CONFIG_NR_DRAM_BANKS);
-			return -ENOMEM;
-		}
+		int ret = rockchip_dram_init_banksize_add_bank(&j, start_addr, size);
 
-		gd->bd->bi_dram[j].start = start_addr;
-		gd->bd->bi_dram[j].size = size;
+		if (ret)
+			return ret;
 	}
 
 	return 0;

-- 
2.47.3

[PATCH 5/5] rockchip: sdram: only reserve BL31 and use mem_map on ARM64

[Aaron Griffith]

This logic to reserve space for BL31 and to add memory holes from
mem_map only makes sense on ARM64. This change simply wraps all of
this logic to only run if CONFIG_ARM64 is enabled. On non-ARM64, it
falls back to accepting memory info from the TPL unmodified.

This is useful on e.g. RK3506, which is not ARM64, but which does
receive memory information from the TPL.

Signed-off-by: Aaron Griffith <aargri@gmail.com>
---
 arch/arm/mach-rockchip/sdram.c | 154 +++++++++++++++++++++--------------------
 1 file changed, 78 insertions(+), 76 deletions(-)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 287073c0e50839cc9366baacbc47512dbe2b4476..82e8e2876f6faca71ff0a8622f08ab3c10a7390a 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -115,103 +115,105 @@ static u32 js_hash(const void *buf, u32 len)
 __weak int rockchip_dram_init_banksize_add_bank(u8 *next_bank, phys_addr_t start_addr,
 						phys_size_t size)
 {
-	struct mm_region *tmp_mem_map = mem_map;
-	phys_addr_t end_addr;
+	if (IS_ENABLED(CONFIG_ARM64)) {
+		struct mm_region *tmp_mem_map = mem_map;
+		phys_addr_t end_addr;
 
-	/*
-	 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
-	 * have it, so force this space as reserved.
-	 */
-	if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
-		size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
-		start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
-	}
-
-	/*
-	 * Put holes for reserved memory areas from mem_map.
-	 *
-	 * Only check for at most one overlap with one reserved memory
-	 * area.
-	 */
-	while (tmp_mem_map->size) {
-		const phys_addr_t rsrv_start = tmp_mem_map->phys;
-		const phys_size_t rsrv_size = tmp_mem_map->size;
-		const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
-
-		/*
-		 * DRAM memories are expected by Arm to be marked as
-		 * Normal Write-back cacheable, Inner shareable[1], so
-		 * let's filter on that to put holes in non-DRAM areas.
-		 *
-		 * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
-		 */
-		const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			PTE_BLOCK_INNER_SHARE;
 		/*
-		 * (AttrIndx | SH) in Lower Attributes of Block
-		 * Descriptor[2].
-		 * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+		 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
+		 * have it, so force this space as reserved.
 		 */
-		const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8);
-
-		if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
-			tmp_mem_map++;
-			continue;
+		if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
+			size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
+			start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
 		}
 
 		/*
-		 * If the start of the DDR_MEM tag is in a reserved
-		 * memory area, move start address and resize.
+		 * Put holes for reserved memory areas from mem_map.
+		 *
+		 * Only check for at most one overlap with one reserved memory
+		 * area.
 		 */
-		if (start_addr >= rsrv_start && start_addr < rsrv_end) {
-			if (rsrv_end - start_addr > size) {
-				debug("Would be negative memory size\n");
-				return -EINVAL;
-			}
-
-			size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
-			start_addr = rsrv_end;
-			break;
-		}
+		while (tmp_mem_map->size) {
+			const phys_addr_t rsrv_start = tmp_mem_map->phys;
+			const phys_size_t rsrv_size = tmp_mem_map->size;
+			const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
 
-		if (start_addr < rsrv_start) {
-			end_addr = start_addr + size;
+			/*
+			 * DRAM memories are expected by Arm to be marked as
+			 * Normal Write-back cacheable, Inner shareable[1], so
+			 * let's filter on that to put holes in non-DRAM areas.
+			 *
+			 * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
+			 */
+			const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE;
+			/*
+			 * (AttrIndx | SH) in Lower Attributes of Block
+			 * Descriptor[2].
+			 * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+			 */
+			const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8);
 
-			if (end_addr <= rsrv_start) {
+			if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
 				tmp_mem_map++;
 				continue;
 			}
 
 			/*
-			 * If the memory area overlaps a reserved memory
-			 * area with start address outside of reserved
-			 * memory area and...
-			 *
-			 * ... ends in the middle of reserved memory
-			 * area, resize.
+			 * If the start of the DDR_MEM tag is in a reserved
+			 * memory area, move start address and resize.
 			 */
-			if (end_addr <= rsrv_end) {
-				size = rsrv_start - start_addr;
+			if (start_addr >= rsrv_start && start_addr < rsrv_end) {
+				if (rsrv_end - start_addr > size) {
+					debug("Would be negative memory size\n");
+					return -EINVAL;
+				}
+
+				size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
+				start_addr = rsrv_end;
 				break;
 			}
 
-			/*
-			 * ... ends after the reserved memory area,
-			 * split the region in two, one for before the
-			 * reserved memory area and one for after.
-			 */
-			gd->bd->bi_dram[*next_bank].start = start_addr;
-			gd->bd->bi_dram[*next_bank].size = rsrv_start - start_addr;
+			if (start_addr < rsrv_start) {
+				end_addr = start_addr + size;
+
+				if (end_addr <= rsrv_start) {
+					tmp_mem_map++;
+					continue;
+				}
+
+				/*
+				 * If the memory area overlaps a reserved memory
+				 * area with start address outside of reserved
+				 * memory area and...
+				 *
+				 * ... ends in the middle of reserved memory
+				 * area, resize.
+				 */
+				if (end_addr <= rsrv_end) {
+					size = rsrv_start - start_addr;
+					break;
+				}
+
+				/*
+				 * ... ends after the reserved memory area,
+				 * split the region in two, one for before the
+				 * reserved memory area and one for after.
+				 */
+				gd->bd->bi_dram[*next_bank].start = start_addr;
+				gd->bd->bi_dram[*next_bank].size = rsrv_start - start_addr;
+
+				*next_bank += 1;
+
+				size = end_addr - rsrv_end;
+				start_addr = rsrv_end;
 
-			*next_bank += 1;
-
-			size = end_addr - rsrv_end;
-			start_addr = rsrv_end;
+				break;
+			}
 
-			break;
+			tmp_mem_map++;
 		}
-
-		tmp_mem_map++;
 	}
 
 	if (*next_bank > CONFIG_NR_DRAM_BANKS) {

-- 
2.47.3

Re: [PATCH 0/5] rockchip: sdram: allow reading memory info from TPL on non-ARM64

[Jonas Karlman]

Hi Aaron,

On 12/29/2025 1:05 AM, Aaron Griffith wrote:
> The RK3506 TPL provides memory info to the bootloader via ATAGS. There
> is already an implementation that reads this information on RK3588 and
> others, but it is currently gated behind CONFIG_ARM64. The RK3506 is
> *not* ARM64.

Use of the RK ATAGS was initially only introduced in mainline U-Boot due
to a memory hole on RK3588 devices with more than 16 GiB DRAM. With [1]
applied this should no longer really be needed.

Is there anything useful encoded in the RK ATAGS that we need on any
other SoC ? (with the goal of using mainline TF-A and/or OP-TEE)

Use of ramboot also overwrite the RK ATAGS with all zero, so we cannot
expect the atags to always be there, only to assist in some cases.

> 
> This patch series aims to allow this code to be used on non-ARM64, by
> 
>  * adding a new config option to read this info from the TPL,
>  * allowing the ATAGS memory area it uses to be set in config headers,
>  * placing truly ARM64-specific logic behind CONFIG_ARM64.
> 
> I'm working on upstreaming RK3506 support, and this is the first patch
> series of hopefully many in that direction.

Nice!, please also see my rk3506 branch [2] for a mainline u-boot branch
that is mostly just waiting on upstream Linux support before being sent
out. Should have good support for most Luckfox Lyra variants and the
ArmSoM Forge1.

I will shortly rebase the rk3506 branch and can possible send out part
of it now that initial parts for rk3506 has landed in upstream Linux.

[1] https://lore.kernel.org/all/20250802220738.3018910-4-jonas@kwiboo.se/
[2] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commits/rk3506

Regards,
Jonas

> 
> Signed-off-by: Aaron Griffith <aargri@gmail.com>
> ---
> Aaron Griffith (5):
>       rockchip: sdram: add option to read bank information from TPL
>       rockchip: sdram: remove redundant configuration checks
>       rockchip: sdram: allow config headers to override ATAGs location
>       rockchip: sdram: refactor bi_dram logic into separate function
>       rockchip: sdram: only reserve BL31 and use mem_map on ARM64
> 
>  arch/arm/mach-rockchip/Kconfig |  11 +++
>  arch/arm/mach-rockchip/sdram.c | 195 ++++++++++++++++++++++-------------------
>  2 files changed, 118 insertions(+), 88 deletions(-)
> ---
> base-commit: 0f6ff53d55ba254de8a995c2a2f5a313acd40ac7
> change-id: 20251226-rockchip-tpl-use-atags-bf3d14a840ca
> 
> Best regards,

Re: [PATCH 0/5] rockchip: sdram: allow reading memory info from TPL on non-ARM64

[Aaron Griffith]

Hello Jonas!

On Mon, Dec 29, 2025 at 4:49 AM Jonas Karlman <jonas@kwiboo.se> wrote:
> [..]
>
> Is there anything useful encoded in the RK ATAGS that we need on any
> other SoC ? (with the goal of using mainline TF-A and/or OP-TEE)

Not that I know of. I must admit, I'm new to this codebase and so I'm
mostly looking at what code already exists and what the Rockchip fork
does to try and synthesize a solution. The Rockchip fork reads this
info, and it was a simple change, so that felt like the right path.

> Nice!, please also see my rk3506 branch [2] for a mainline u-boot branch
> that is mostly just waiting on upstream Linux support before being sent
> out. Should have good support for most Luckfox Lyra variants and the
> ArmSoM Forge1.

Oh, fantastic! I started working on this as a way to learn my way
around U-boot, but I've been learning that adding RK3506 support might
have been ambitious. What I have boots just fine and I learned a lot,
but... more experience here is definitely for the best.

(Your link [2] to your rk3506 branch is a 403 for me. Is that temporary,
or..?)

I'm happy to either continue with these patches if they seem useful
for any other reason, or to drop them if not. RK3506 is the only
reason I had for them myself.

Thanks,
 -Aaron

Re: [PATCH 0/5] rockchip: sdram: allow reading memory info from TPL on non-ARM64

[Jonas Karlman]

Hi Aaron,

On 12/29/2025 11:26 AM, Aaron Griffith wrote:
> Hello Jonas!
> 
> On Mon, Dec 29, 2025 at 4:49 AM Jonas Karlman <jonas@kwiboo.se> wrote:
>> [..]
>>
>> Is there anything useful encoded in the RK ATAGS that we need on any
>> other SoC ? (with the goal of using mainline TF-A and/or OP-TEE)
> 
> Not that I know of. I must admit, I'm new to this codebase and so I'm
> mostly looking at what code already exists and what the Rockchip fork
> does to try and synthesize a solution. The Rockchip fork reads this
> info, and it was a simple change, so that felt like the right path.

The memory size info is also encoded in PMUGRF os_reg2 reg, a simple
call to rockchip_sdram_size(PMUGRF_BASE + OS_REG2_REG) should be enough
to get the memory size info typically needed by U-Boot.

The RK ATAGS do include some other information that could be useful e.g.
what uartX and baudrate is used by external TPL, but this is mostly
information that the vendor blobs for TPL, SPL, TF-A and OP-TEE read,
use and/or update.

For mainline U-Boot there should not really be a need for using the info
encoded using the vendor RK ATAGS, at least no to my knowledge.

>> Nice!, please also see my rk3506 branch [2] for a mainline u-boot branch
>> that is mostly just waiting on upstream Linux support before being sent
>> out. Should have good support for most Luckfox Lyra variants and the
>> ArmSoM Forge1.
> 
> Oh, fantastic! I started working on this as a way to learn my way
> around U-boot, but I've been learning that adding RK3506 support might
> have been ambitious. What I have boots just fine and I learned a lot,
> but... more experience here is definitely for the best.
> 
> (Your link [2] to your rk3506 branch is a 403 for me. Is that temporary,
> or..?)

Strange, probably the Anubis instance used by source.denx.de at fault.

I have now pushed an updated rk3506 branch to GitHub [1], the old branch
last rebased in September is located at [2].

Most of my RK3506 work was done back in February, not sure all features
was fully implemented, e.g. Ethernet on my Forge1 did not seem to work
now that I did a new runtime test, maybe a PHY driver is missing.

[1] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3506
[2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3506-2025091

> 
> I'm happy to either continue with these patches if they seem useful
> for any other reason, or to drop them if not. RK3506 is the only
> reason I had for them myself.

I do not think we want to extend the use of the RK ATAGS, at least not
unless it is absolutely needed.

There is still one big question related to RK3506 that needs to be
figured out, should we use cpu enable-method psci and offload psci to
e.g. OP-TEE as done by vendor, or possible TF-A or fully handle this in
kernel?

Hopefully that and a basic device tree can be submitted and merged to
mainline Linux in a near future, after that we have a proper DT that can
be used by U-Boot. At least this is what I have been waiting on :-)

Regards,
Jonas

> Thanks,
>  -Aaron
> 

Re: [PATCH 0/5] rockchip: sdram: allow reading memory info from TPL on non-ARM64

[Aaron Griffith]

Hello Jonas,

On Mon, Dec 29, 2025 at 08:15:29PM +0100, Jonas Karlman wrote:
> I do not think we want to extend the use of the RK ATAGS, at least not
> unless it is absolutely needed.

Understood, please ignore these patches then.

> The memory size info is also encoded in PMUGRF os_reg2 reg, a simple
> call to rockchip_sdram_size(PMUGRF_BASE + OS_REG2_REG) should be enough
> to get the memory size info typically needed by U-Boot.

I got this working, but I got stuck on the code in
`dram_init_banksize` that tries to read reserved memory from
OP-TEE. When left unmodified it mangles the ram banks and tells Linux
it has 4GB+ of memory. So, I was looking for a way around that.

I was also not aware that it's possible to tell the Rockchip TPL where
to load the SPL. OP-TEE at 0x1000 was giving me a lot of grief.

Besides these two issues, I'm actually quite happy to see that my
branch matches yours pretty well, for my first attempt.

> I have now pushed an updated rk3506 branch to GitHub [1], the old branch
> last rebased in September is located at [2].

Thanks! I'm watching this and the kernel developments closely.

FWIW, I have some Debian images for the Lyra boards [1]. Not very
complicated, but I didn't see any options for Lyra besides the
vendor's SDK. I plan on swapping in upstream sources as they become
ready.

 [1]: https://github.com/agrif/debian-lyra

Thanks,
 -Aaron