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Wed, 29 Apr 2026 09:20:56 -0700 (PDT) Received: from jernej-laptop.localnet ([188.159.248.16]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-447b7217c56sm6742489f8f.20.2026.04.29.09.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 09:20:56 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: u-boot@lists.denx.de, Yixun Lan Cc: linux-sunxi@lists.linux.dev, Andre Przywara , Jagan Teki , Tom Rini , Yixun Lan Subject: Re: [PATCH] spi: sunxi: wait for TX/RX fifo reset done Date: Wed, 29 Apr 2026 18:20:54 +0200 Message-ID: In-Reply-To: <20260421-02-spi-fifo-reset-v1-1-e2cdd4bd474d@gentoo.org> References: <20260421-02-spi-fifo-reset-v1-1-e2cdd4bd474d@gentoo.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Dne torek, 21. april 2026 ob 06:47:50 Srednjeevropski poletni =C4=8Das je Y= ixun Lan napisal(a): > Once reset SPI TX or RX fifo, the underlying hardware need to take > some time to actually settle down, the two bits will automatically > clear to 0, so use a poll mechanism to check status bits to make sure > it's done correctly. >=20 > Signed-off-by: Yixun Lan > --- > On Cubie A7A board which using A733 SoC, we encoutered a SPI nor flash > timeout issue, it turns out that the SPI fifo reset take a few time to > settle down, Add a loop to poll the status. >=20 > This was the error message shows on A7A board once this issue happened. >=20 > =3D> sf probe > ERROR: sun4i_spi: Timeout transferring data > Failed to initialize SPI flash at 0:0 (error -2) Reviewed-by: Jernej Skrabec Best regards, Jernej