* [PATCH] clk/qcom: sc7280: add more QUP clocks
@ 2026-01-08 19:49 Casey Connolly
2026-01-16 7:28 ` Sumit Garg
2026-01-16 18:03 ` Casey Connolly
0 siblings, 2 replies; 3+ messages in thread
From: Casey Connolly @ 2026-01-08 19:49 UTC (permalink / raw)
To: Casey Connolly, Luca Weiss, Lukasz Majewski, Neil Armstrong,
Sumit Garg, Tom Rini
Cc: u-boot-qcom, Sumit Garg, u-boot
Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
---
drivers/clk/qcom/clock-sc7280.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 55a233df3945..7b6ed8260236 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -62,8 +62,13 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
if (clk->id < priv->data->num_clks)
debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
switch (clk->id) {
+ case GCC_QUPV3_WRAP0_S2_CLK: /* UART2 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x17270,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
case GCC_QUPV3_WRAP0_S5_CLK: /* UART5 */
freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, 0x17600,
freq->pre_div, freq->m, freq->n, freq->src, 16);
@@ -131,11 +136,15 @@ static const struct gate_clk sc7280_clks[] = {
GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x52008, BIT(12)),
GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x52008, BIT(14)),
GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(15)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, BIT(16)),
GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, BIT(17)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)),
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),
@@ -189,8 +198,11 @@ static int sc7280_enable(struct clk *clk)
break;
case GCC_QUPV3_WRAP0_S3_CLK:
clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
break;
+ case GCC_QUPV3_WRAP1_S1_CLK:
+ clk_rcg_set_rate_mnd(priv->base, 0x18140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+ break;
}
return qcom_gate_clk_en(priv, clk->id);
}
--
2.51.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] clk/qcom: sc7280: add more QUP clocks
2026-01-08 19:49 [PATCH] clk/qcom: sc7280: add more QUP clocks Casey Connolly
@ 2026-01-16 7:28 ` Sumit Garg
2026-01-16 18:03 ` Casey Connolly
1 sibling, 0 replies; 3+ messages in thread
From: Sumit Garg @ 2026-01-16 7:28 UTC (permalink / raw)
To: Casey Connolly
Cc: Luca Weiss, Lukasz Majewski, Neil Armstrong, Tom Rini,
u-boot-qcom, Sumit Garg, u-boot
On Thu, Jan 08, 2026 at 08:49:55PM +0100, Casey Connolly wrote:
> Add more clocks for UART2, i2c9 and a few others. This is enough to get
> the rubikpi 3 working.
>
> Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
> ---
> drivers/clk/qcom/clock-sc7280.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
Good to see rubikpi 3 support coming in, I suppose the DT will be
available in next U-Boot DT sync.
FWIW:
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
> index 55a233df3945..7b6ed8260236 100644
> --- a/drivers/clk/qcom/clock-sc7280.c
> +++ b/drivers/clk/qcom/clock-sc7280.c
> @@ -62,8 +62,13 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
> if (clk->id < priv->data->num_clks)
> debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
>
> switch (clk->id) {
> + case GCC_QUPV3_WRAP0_S2_CLK: /* UART2 */
> + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x17270,
> + freq->pre_div, freq->m, freq->n, freq->src, 16);
> + return freq->freq;
> case GCC_QUPV3_WRAP0_S5_CLK: /* UART5 */
> freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
> clk_rcg_set_rate_mnd(priv->base, 0x17600,
> freq->pre_div, freq->m, freq->n, freq->src, 16);
> @@ -131,11 +136,15 @@ static const struct gate_clk sc7280_clks[] = {
> GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
> GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
> GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
> GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x52008, BIT(12)),
> GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x52008, BIT(14)),
> GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(15)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, BIT(16)),
> GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, BIT(17)),
> + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)),
> GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
> GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
> GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
> GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),
> @@ -189,8 +198,11 @@ static int sc7280_enable(struct clk *clk)
> break;
> case GCC_QUPV3_WRAP0_S3_CLK:
> clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> break;
> + case GCC_QUPV3_WRAP1_S1_CLK:
> + clk_rcg_set_rate_mnd(priv->base, 0x18140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> + break;
> }
>
> return qcom_gate_clk_en(priv, clk->id);
> }
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] clk/qcom: sc7280: add more QUP clocks
2026-01-08 19:49 [PATCH] clk/qcom: sc7280: add more QUP clocks Casey Connolly
2026-01-16 7:28 ` Sumit Garg
@ 2026-01-16 18:03 ` Casey Connolly
1 sibling, 0 replies; 3+ messages in thread
From: Casey Connolly @ 2026-01-16 18:03 UTC (permalink / raw)
To: Luca Weiss, Lukasz Majewski, Neil Armstrong, Sumit Garg, Tom Rini,
Casey Connolly
Cc: u-boot-qcom, Sumit Garg, u-boot
On Thu, 08 Jan 2026 20:49:55 +0100, Casey Connolly wrote:
> Add more clocks for UART2, i2c9 and a few others. This is enough to get
> the rubikpi 3 working.
>
>
Applied, thanks!
[1/1] clk/qcom: sc7280: add more QUP clocks
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/142df62cb68d
Best regards,
--
// Casey (she/they)
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-01-16 18:05 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-08 19:49 [PATCH] clk/qcom: sc7280: add more QUP clocks Casey Connolly
2026-01-16 7:28 ` Sumit Garg
2026-01-16 18:03 ` Casey Connolly
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox