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charset=us-ascii Content-Disposition: inline In-Reply-To: <20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Tue, Jan 13, 2026 at 12:28:55PM +0530, Balaji Selvanathan wrote: > Correct USB30 primary clock RCG configuration and add missing > USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration. > Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") > > Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition. > Extend reset map with USB-related BCR entries and video BCR > for comprehensive reset control support. > > Signed-off-by: Balaji Selvanathan > --- > drivers/clk/qcom/clock-sa8775p.c | 28 ++++++++++++++++++++++++---- > 1 file changed, 24 insertions(+), 4 deletions(-) With the indentation fixes, feel free to add: Acked-by: Sumit Garg -Sumit > > diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c > index 5a6fbd417ff..25c8cd4af9a 100644 > --- a/drivers/clk/qcom/clock-sa8775p.c > +++ b/drivers/clk/qcom/clock-sa8775p.c > @@ -15,8 +15,9 @@ > #include > #include "clock-qcom.h" > > -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 > -#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 > +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1b040 > +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028 > +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c > > #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) > #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) > @@ -59,8 +60,8 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) > case GCC_USB30_PRIM_MASTER_CLK: > WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); > clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, > - 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); > - clk_rcg_set_rate(priv->base, 0xf064, 0, 0); > + 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); > + clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); > return rate; > default: > return 0; > @@ -75,6 +76,7 @@ static const struct gate_clk sa8775p_clks[] = { > GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), > GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), > GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), > + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1), > > /* QUP Wrapper 0 clocks */ > GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), > @@ -157,6 +159,24 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = { > [GCC_TSCSS_BCR] = { 0x21000 }, > [GCC_UFS_CARD_BCR] = { 0x81000 }, > [GCC_UFS_PHY_BCR] = { 0x83000 }, > + [GCC_USB20_PRIM_BCR] = {0x1c000}, > + [GCC_USB2_PHY_PRIM_BCR] = {0x5c028}, > + [GCC_USB2_PHY_SEC_BCR] = {0x5c02c}, > + [GCC_USB30_PRIM_BCR] = {0x1b000}, > + [GCC_USB30_SEC_BCR] = {0x2f000}, > + [GCC_USB3_DP_PHY_PRIM_BCR] = {0x5c008}, > + [GCC_USB3_DP_PHY_SEC_BCR] = {0x5c014}, > + [GCC_USB3_PHY_PRIM_BCR] = {0x5c000}, > + [GCC_USB3_PHY_SEC_BCR] = {0x5c00c}, > + [GCC_USB3_PHY_TERT_BCR] = {0x5c030}, > + [GCC_USB3_UNIPHY_MP0_BCR] = {0x5c018}, > + [GCC_USB3_UNIPHY_MP1_BCR] = {0x5c01c}, > + [GCC_USB3PHY_PHY_PRIM_BCR] = {0x5c004}, > + [GCC_USB3PHY_PHY_SEC_BCR] = {0x5c010}, > + [GCC_USB3UNIPHY_PHY_MP0_BCR] = {0x5c020}, > + [GCC_USB3UNIPHY_PHY_MP1_BCR] = {0x5c024}, > + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = {0x76000}, > + [GCC_VIDEO_BCR] = {0x34000} > }; > > static const struct qcom_power_map sa8775p_gdscs[] = { > -- > 2.34.1 >