* [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets
@ 2026-01-13 6:58 Balaji Selvanathan
2026-01-13 7:54 ` Varadarajan Narayanan
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Balaji Selvanathan @ 2026-01-13 6:58 UTC (permalink / raw)
To: lukma, casey.connolly, neil.armstrong, sumit.garg, trini,
balaji.selvanathan, swathi.tamilselvan, quic_varada, u-boot-qcom,
u-boot
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
drivers/clk/qcom/clock-sa8775p.c | 28 ++++++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index 5a6fbd417ff..25c8cd4af9a 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -15,8 +15,9 @@
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include "clock-qcom.h"
-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
-#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1b040
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028
+#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c
#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
@@ -59,8 +60,8 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
case GCC_USB30_PRIM_MASTER_CLK:
WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
- 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
- clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
+ 5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
+ clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
return rate;
default:
return 0;
@@ -75,6 +76,7 @@ static const struct gate_clk sa8775p_clks[] = {
GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
+ GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1),
/* QUP Wrapper 0 clocks */
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
@@ -157,6 +159,24 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = {
[GCC_TSCSS_BCR] = { 0x21000 },
[GCC_UFS_CARD_BCR] = { 0x81000 },
[GCC_UFS_PHY_BCR] = { 0x83000 },
+ [GCC_USB20_PRIM_BCR] = {0x1c000},
+ [GCC_USB2_PHY_PRIM_BCR] = {0x5c028},
+ [GCC_USB2_PHY_SEC_BCR] = {0x5c02c},
+ [GCC_USB30_PRIM_BCR] = {0x1b000},
+ [GCC_USB30_SEC_BCR] = {0x2f000},
+ [GCC_USB3_DP_PHY_PRIM_BCR] = {0x5c008},
+ [GCC_USB3_DP_PHY_SEC_BCR] = {0x5c014},
+ [GCC_USB3_PHY_PRIM_BCR] = {0x5c000},
+ [GCC_USB3_PHY_SEC_BCR] = {0x5c00c},
+ [GCC_USB3_PHY_TERT_BCR] = {0x5c030},
+ [GCC_USB3_UNIPHY_MP0_BCR] = {0x5c018},
+ [GCC_USB3_UNIPHY_MP1_BCR] = {0x5c01c},
+ [GCC_USB3PHY_PHY_PRIM_BCR] = {0x5c004},
+ [GCC_USB3PHY_PHY_SEC_BCR] = {0x5c010},
+ [GCC_USB3UNIPHY_PHY_MP0_BCR] = {0x5c020},
+ [GCC_USB3UNIPHY_PHY_MP1_BCR] = {0x5c024},
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = {0x76000},
+ [GCC_VIDEO_BCR] = {0x34000}
};
static const struct qcom_power_map sa8775p_gdscs[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets
2026-01-13 6:58 [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets Balaji Selvanathan
@ 2026-01-13 7:54 ` Varadarajan Narayanan
2026-01-16 10:04 ` Sumit Garg
2026-01-16 18:03 ` Casey Connolly
2 siblings, 0 replies; 4+ messages in thread
From: Varadarajan Narayanan @ 2026-01-13 7:54 UTC (permalink / raw)
To: Balaji Selvanathan
Cc: lukma, casey.connolly, neil.armstrong, sumit.garg, trini,
swathi.tamilselvan, quic_varada, u-boot-qcom, u-boot
On Tue, Jan 13, 2026 at 12:28:55PM +0530, Balaji Selvanathan wrote:
> Correct USB30 primary clock RCG configuration and add missing
> USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
> Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
>
> Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
> Extend reset map with USB-related BCR entries and video BCR
> for comprehensive reset control support.
>
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
> drivers/clk/qcom/clock-sa8775p.c | 28 ++++++++++++++++++++++++----
> 1 file changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
> index 5a6fbd417ff..25c8cd4af9a 100644
> --- a/drivers/clk/qcom/clock-sa8775p.c
> +++ b/drivers/clk/qcom/clock-sa8775p.c
> @@ -15,8 +15,9 @@
> #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> #include "clock-qcom.h"
>
> -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> -#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1b040
> +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028
> +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c
>
> #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
> #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
> @@ -59,8 +60,8 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
> case GCC_USB30_PRIM_MASTER_CLK:
> WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
> clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> - 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
> - clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
> + 5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
Indentation seems to be off.
-Varada
> + clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
> return rate;
> default:
> return 0;
> @@ -75,6 +76,7 @@ static const struct gate_clk sa8775p_clks[] = {
> GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
> GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
> GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
> + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1),
>
> /* QUP Wrapper 0 clocks */
> GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
> @@ -157,6 +159,24 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = {
> [GCC_TSCSS_BCR] = { 0x21000 },
> [GCC_UFS_CARD_BCR] = { 0x81000 },
> [GCC_UFS_PHY_BCR] = { 0x83000 },
> + [GCC_USB20_PRIM_BCR] = {0x1c000},
> + [GCC_USB2_PHY_PRIM_BCR] = {0x5c028},
> + [GCC_USB2_PHY_SEC_BCR] = {0x5c02c},
> + [GCC_USB30_PRIM_BCR] = {0x1b000},
> + [GCC_USB30_SEC_BCR] = {0x2f000},
> + [GCC_USB3_DP_PHY_PRIM_BCR] = {0x5c008},
> + [GCC_USB3_DP_PHY_SEC_BCR] = {0x5c014},
> + [GCC_USB3_PHY_PRIM_BCR] = {0x5c000},
> + [GCC_USB3_PHY_SEC_BCR] = {0x5c00c},
> + [GCC_USB3_PHY_TERT_BCR] = {0x5c030},
> + [GCC_USB3_UNIPHY_MP0_BCR] = {0x5c018},
> + [GCC_USB3_UNIPHY_MP1_BCR] = {0x5c01c},
> + [GCC_USB3PHY_PHY_PRIM_BCR] = {0x5c004},
> + [GCC_USB3PHY_PHY_SEC_BCR] = {0x5c010},
> + [GCC_USB3UNIPHY_PHY_MP0_BCR] = {0x5c020},
> + [GCC_USB3UNIPHY_PHY_MP1_BCR] = {0x5c024},
> + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = {0x76000},
> + [GCC_VIDEO_BCR] = {0x34000}
> };
>
> static const struct qcom_power_map sa8775p_gdscs[] = {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets
2026-01-13 6:58 [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets Balaji Selvanathan
2026-01-13 7:54 ` Varadarajan Narayanan
@ 2026-01-16 10:04 ` Sumit Garg
2026-01-16 18:03 ` Casey Connolly
2 siblings, 0 replies; 4+ messages in thread
From: Sumit Garg @ 2026-01-16 10:04 UTC (permalink / raw)
To: Balaji Selvanathan
Cc: lukma, casey.connolly, neil.armstrong, trini, swathi.tamilselvan,
quic_varada, u-boot-qcom, u-boot
On Tue, Jan 13, 2026 at 12:28:55PM +0530, Balaji Selvanathan wrote:
> Correct USB30 primary clock RCG configuration and add missing
> USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
> Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
>
> Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
> Extend reset map with USB-related BCR entries and video BCR
> for comprehensive reset control support.
>
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
> drivers/clk/qcom/clock-sa8775p.c | 28 ++++++++++++++++++++++++----
> 1 file changed, 24 insertions(+), 4 deletions(-)
With the indentation fixes, feel free to add:
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
> index 5a6fbd417ff..25c8cd4af9a 100644
> --- a/drivers/clk/qcom/clock-sa8775p.c
> +++ b/drivers/clk/qcom/clock-sa8775p.c
> @@ -15,8 +15,9 @@
> #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> #include "clock-qcom.h"
>
> -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> -#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0x1b040
> +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028
> +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c
>
> #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
> #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
> @@ -59,8 +60,8 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
> case GCC_USB30_PRIM_MASTER_CLK:
> WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
> clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> - 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
> - clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
> + 5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
> + clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
> return rate;
> default:
> return 0;
> @@ -75,6 +76,7 @@ static const struct gate_clk sa8775p_clks[] = {
> GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
> GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
> GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
> + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1),
>
> /* QUP Wrapper 0 clocks */
> GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
> @@ -157,6 +159,24 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = {
> [GCC_TSCSS_BCR] = { 0x21000 },
> [GCC_UFS_CARD_BCR] = { 0x81000 },
> [GCC_UFS_PHY_BCR] = { 0x83000 },
> + [GCC_USB20_PRIM_BCR] = {0x1c000},
> + [GCC_USB2_PHY_PRIM_BCR] = {0x5c028},
> + [GCC_USB2_PHY_SEC_BCR] = {0x5c02c},
> + [GCC_USB30_PRIM_BCR] = {0x1b000},
> + [GCC_USB30_SEC_BCR] = {0x2f000},
> + [GCC_USB3_DP_PHY_PRIM_BCR] = {0x5c008},
> + [GCC_USB3_DP_PHY_SEC_BCR] = {0x5c014},
> + [GCC_USB3_PHY_PRIM_BCR] = {0x5c000},
> + [GCC_USB3_PHY_SEC_BCR] = {0x5c00c},
> + [GCC_USB3_PHY_TERT_BCR] = {0x5c030},
> + [GCC_USB3_UNIPHY_MP0_BCR] = {0x5c018},
> + [GCC_USB3_UNIPHY_MP1_BCR] = {0x5c01c},
> + [GCC_USB3PHY_PHY_PRIM_BCR] = {0x5c004},
> + [GCC_USB3PHY_PHY_SEC_BCR] = {0x5c010},
> + [GCC_USB3UNIPHY_PHY_MP0_BCR] = {0x5c020},
> + [GCC_USB3UNIPHY_PHY_MP1_BCR] = {0x5c024},
> + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = {0x76000},
> + [GCC_VIDEO_BCR] = {0x34000}
> };
>
> static const struct qcom_power_map sa8775p_gdscs[] = {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets
2026-01-13 6:58 [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets Balaji Selvanathan
2026-01-13 7:54 ` Varadarajan Narayanan
2026-01-16 10:04 ` Sumit Garg
@ 2026-01-16 18:03 ` Casey Connolly
2 siblings, 0 replies; 4+ messages in thread
From: Casey Connolly @ 2026-01-16 18:03 UTC (permalink / raw)
To: lukma, neil.armstrong, sumit.garg, trini, swathi.tamilselvan,
quic_varada, u-boot-qcom, u-boot, Balaji Selvanathan
On Tue, 13 Jan 2026 12:28:55 +0530, Balaji Selvanathan wrote:
> Correct USB30 primary clock RCG configuration and add missing
> USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
> Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
>
> Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
> Extend reset map with USB-related BCR entries and video BCR
> for comprehensive reset control support.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: sa8775p: Fix USB clock configuration and add resets
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/f4886799a0af
Best regards,
--
// Casey (she/they)
^ permalink raw reply [flat|nested] 4+ messages in thread
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2026-01-13 6:58 [PATCH v1] clk: qcom: sa8775p: Fix USB clock configuration and add resets Balaji Selvanathan
2026-01-13 7:54 ` Varadarajan Narayanan
2026-01-16 10:04 ` Sumit Garg
2026-01-16 18:03 ` Casey Connolly
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