[PATCH v1 0/3] Enable eMMC/SDCC support for QCS615 platform

[PATCH v1 0/3] Enable eMMC/SDCC support for QCS615 platform

[Balaji Selvanathan]

This series enables eMMC functionality on QCS615 platform by adding
the necessary clock infrastructure, removing conflicting device tree
fixups, and updating the boot environment to work reliably with eMMC
storage.

Balaji Selvanathan (3):
  clk: qcom: Add QCS615 SDCC clock support and RPMH-CLK compatibility
  arm: snapdragon: Remove QCS615 MMC node disable fixup
  board: qualcomm: Remove SCSI scan from default preboot environment

 arch/arm/mach-snapdragon/of_fixup.c | 14 --------------
 board/qualcomm/default.env          |  2 +-
 drivers/clk/clk-stub.c              |  2 +-
 drivers/clk/qcom/clock-qcom.h       |  1 +
 drivers/clk/qcom/clock-qcs615.c     | 10 ++++++++++
 5 files changed, 13 insertions(+), 16 deletions(-)

-- 
2.34.1

[PATCH v1 1/3] clk: qcom: Add QCS615 SDCC clock support and RPMH-CLK compatibility

[Balaji Selvanathan]

Add SDCC (SD Card Controller) clock support for QCS615 platform to
enable eMMC functionality. This includes adding SDCC1 and SDCC2 clock
gates, implementing SDCC1 apps clock rate configuration
and adding QCS615 RPMH clock compatibility to the stub
driver to handle device tree clock controller references.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/clk/clk-stub.c          |  2 +-
 drivers/clk/qcom/clock-qcom.h   |  1 +
 drivers/clk/qcom/clock-qcs615.c | 10 ++++++++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 117266ac778..1bc749e47b3 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = {
 
 static const struct udevice_id stub_clk_ids[] = {
 	{ .compatible = "qcom,rpmcc" },
+	{ .compatible = "qcom,qcs615-rpmh-clk" },
 	{ .compatible = "qcom,sdm670-rpmh-clk" },
 	{ .compatible = "qcom,sdm845-rpmh-clk" },
 	{ .compatible = "qcom,sc7180-rpmh-clk" },
@@ -69,4 +70,3 @@ U_BOOT_DRIVER(clk_stub) = {
 	.of_match = stub_clk_ids,
 	.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
-
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 3a4550d8536..bc7e0453cba 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -14,6 +14,7 @@
 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
 #define CFG_CLK_SRC_GPLL2 (2 << 8)
 #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)
+#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8)
 #define CFG_CLK_SRC_GPLL9 (2 << 8)
 #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
 #define CFG_CLK_SRC_GPLL6 (4 << 8)
diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
index 4700baba8c9..483642531ef 100644
--- a/drivers/clk/qcom/clock-qcs615.c
+++ b/drivers/clk/qcom/clock-qcs615.c
@@ -18,6 +18,7 @@
 #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR	0xf034
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0xf01c
 #define USB3_PRIM_PHY_AUX_CMD_RCGR		0xf060
+#define SDCC1_APPS_CLK_CMD_RCGR			0x12028
 
 #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
 #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
@@ -52,6 +53,10 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
 				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
 		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
 		return rate;
+	case GCC_SDCC1_APPS_CLK:
+		clk_rcg_set_rate(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
+				 1, CFG_CLK_SRC_GPLL6_OUT_MAIN);
+		return rate;
 	default:
 		return 0;
 	}
@@ -66,6 +71,11 @@ static const struct gate_clk qcs615_clks[] = {
 	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
 	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
 	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
+	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),
+	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)),
+	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)),
+	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
+	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
 	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
-- 
2.34.1

[PATCH v1 2/3] arm: snapdragon: Remove QCS615 MMC node disable fixup

[Balaji Selvanathan]

Remove the QCS615-specific device tree fixup that was disabling the
MMC node at /soc@0/mmc@7c4000. This fixup is no longer needed as the
MMC/SDCC functionality should now be properly supported through the
clock infrastructure and device tree configuration.

This patch is based on the changes in the upstream submission:
https://lore.kernel.org/u-boot/20260113115404.1448759-4-aswin.murugan@oss.qualcomm.com/

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 arch/arm/mach-snapdragon/of_fixup.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c
index 9b6e1847489..216cc816d95 100644
--- a/arch/arm/mach-snapdragon/of_fixup.c
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -194,20 +194,6 @@ EVENT_SPY_FULL(EVT_OF_LIVE_BUILT, qcom_of_fixup_nodes);
 static void soc_specific_fixups(struct fdt_header *fdt)
 {
 	int ret;
-
-	/* QCS615-specific fixup: Disable MMC node */
-	if (fdt_node_check_compatible(fdt, 0, "qcom,qcs615") == 0) {
-		int path_offset;
-		char prop_val[] = "disabled";
-
-		path_offset = fdt_path_offset(fdt, "/soc@0/mmc@7c4000");
-		if (path_offset >= 0) {
-			ret = fixup_dt_node(fdt, path_offset, "status",
-					    (void *)prop_val, SET_PROP_STRING);
-			if (ret)
-				log_err("Failed to disable MMC node for QCS615: %d\n", ret);
-		}
-	}
 }
 
 int ft_board_setup(void __maybe_unused *blob, struct bd_info __maybe_unused *bd)
-- 
2.34.1

[PATCH v1 3/3] board: qualcomm: Remove SCSI scan from default preboot environment

[Balaji Selvanathan]

Remove "scsi scan" from the preboot command sequence in the default
Qualcomm board environment. The SCSI scan command fails on eMMC-based
boot configurations, causing unnecessary boot delays and potential
error messages during the preboot phase.

This change improves boot reliability on platforms using eMMC storage
as the primary boot device.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 board/qualcomm/default.env | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/qualcomm/default.env b/board/qualcomm/default.env
index dbf6f4e7260..7cfa8e0ce2a 100644
--- a/board/qualcomm/default.env
+++ b/board/qualcomm/default.env
@@ -1,7 +1,7 @@
 stdin=serial,button-kbd
 stdout=serial,vidconsole
 stderr=serial,vidconsole
-preboot=scsi scan; usb start
+preboot=usb start
 fastboot=fastboot -l $fastboot_addr_r usb 0
 do_boot=bootefi bootmgr
 bootmenu_0=Boot first available device=run do_boot
-- 
2.34.1

Re: [PATCH v1 1/3] clk: qcom: Add QCS615 SDCC clock support and RPMH-CLK compatibility

[Sumit Garg]

On Mon, Jan 26, 2026 at 09:29:36PM +0530, Balaji Selvanathan wrote:
> Add SDCC (SD Card Controller) clock support for QCS615 platform to
> enable eMMC functionality. This includes adding SDCC1 and SDCC2 clock
> gates, implementing SDCC1 apps clock rate configuration
> and adding QCS615 RPMH clock compatibility to the stub
> driver to handle device tree clock controller references.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/clk/clk-stub.c          |  2 +-
>  drivers/clk/qcom/clock-qcom.h   |  1 +
>  drivers/clk/qcom/clock-qcs615.c | 10 ++++++++++
>  3 files changed, 12 insertions(+), 1 deletion(-)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> 
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index 117266ac778..1bc749e47b3 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = {
>  
>  static const struct udevice_id stub_clk_ids[] = {
>  	{ .compatible = "qcom,rpmcc" },
> +	{ .compatible = "qcom,qcs615-rpmh-clk" },
>  	{ .compatible = "qcom,sdm670-rpmh-clk" },
>  	{ .compatible = "qcom,sdm845-rpmh-clk" },
>  	{ .compatible = "qcom,sc7180-rpmh-clk" },
> @@ -69,4 +70,3 @@ U_BOOT_DRIVER(clk_stub) = {
>  	.of_match = stub_clk_ids,
>  	.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
>  };
> -
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 3a4550d8536..bc7e0453cba 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -14,6 +14,7 @@
>  #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
>  #define CFG_CLK_SRC_GPLL2 (2 << 8)
>  #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)
> +#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8)
>  #define CFG_CLK_SRC_GPLL9 (2 << 8)
>  #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
>  #define CFG_CLK_SRC_GPLL6 (4 << 8)
> diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
> index 4700baba8c9..483642531ef 100644
> --- a/drivers/clk/qcom/clock-qcs615.c
> +++ b/drivers/clk/qcom/clock-qcs615.c
> @@ -18,6 +18,7 @@
>  #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR	0xf034
>  #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0xf01c
>  #define USB3_PRIM_PHY_AUX_CMD_RCGR		0xf060
> +#define SDCC1_APPS_CLK_CMD_RCGR			0x12028
>  
>  #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
>  #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
> @@ -52,6 +53,10 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
>  				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
>  		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
>  		return rate;
> +	case GCC_SDCC1_APPS_CLK:
> +		clk_rcg_set_rate(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
> +				 1, CFG_CLK_SRC_GPLL6_OUT_MAIN);
> +		return rate;
>  	default:
>  		return 0;
>  	}
> @@ -66,6 +71,11 @@ static const struct gate_clk qcs615_clks[] = {
>  	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
> -- 
> 2.34.1
> 

Re: [PATCH v1 2/3] arm: snapdragon: Remove QCS615 MMC node disable fixup

[Sumit Garg]

On Mon, Jan 26, 2026 at 09:29:37PM +0530, Balaji Selvanathan wrote:
> Remove the QCS615-specific device tree fixup that was disabling the
> MMC node at /soc@0/mmc@7c4000. This fixup is no longer needed as the
> MMC/SDCC functionality should now be properly supported through the
> clock infrastructure and device tree configuration.
> 
> This patch is based on the changes in the upstream submission:
> https://lore.kernel.org/u-boot/20260113115404.1448759-4-aswin.murugan@oss.qualcomm.com/

Rather drop this patch entirely since fixing eMMC as you did as part of
patch #1 is the right thing to do for upstream. The series you
referenced can be adjusted accordingly.

-Sumit

> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  arch/arm/mach-snapdragon/of_fixup.c | 14 --------------
>  1 file changed, 14 deletions(-)
> 
> diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c
> index 9b6e1847489..216cc816d95 100644
> --- a/arch/arm/mach-snapdragon/of_fixup.c
> +++ b/arch/arm/mach-snapdragon/of_fixup.c
> @@ -194,20 +194,6 @@ EVENT_SPY_FULL(EVT_OF_LIVE_BUILT, qcom_of_fixup_nodes);
>  static void soc_specific_fixups(struct fdt_header *fdt)
>  {
>  	int ret;
> -
> -	/* QCS615-specific fixup: Disable MMC node */
> -	if (fdt_node_check_compatible(fdt, 0, "qcom,qcs615") == 0) {
> -		int path_offset;
> -		char prop_val[] = "disabled";
> -
> -		path_offset = fdt_path_offset(fdt, "/soc@0/mmc@7c4000");
> -		if (path_offset >= 0) {
> -			ret = fixup_dt_node(fdt, path_offset, "status",
> -					    (void *)prop_val, SET_PROP_STRING);
> -			if (ret)
> -				log_err("Failed to disable MMC node for QCS615: %d\n", ret);
> -		}
> -	}
>  }
>  
>  int ft_board_setup(void __maybe_unused *blob, struct bd_info __maybe_unused *bd)
> -- 
> 2.34.1
> 

Re: [PATCH v1 3/3] board: qualcomm: Remove SCSI scan from default preboot environment

[Sumit Garg]

On Mon, Jan 26, 2026 at 09:29:38PM +0530, Balaji Selvanathan wrote:
> Remove "scsi scan" from the preboot command sequence in the default
> Qualcomm board environment.

This is the default environment configuration expected to work on all
Qcom platforms, wouln't it break platforms supporting UFS boot?

> The SCSI scan command fails on eMMC-based
> boot configurations, causing unnecessary boot delays and potential
> error messages during the preboot phase.

Say if UFS isn't supported as the boot target then this SCSI scan should
just bail out. Can you share the error messages and boot delays seen
here?

-Sumit

> 
> This change improves boot reliability on platforms using eMMC storage
> as the primary boot device.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  board/qualcomm/default.env | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/qualcomm/default.env b/board/qualcomm/default.env
> index dbf6f4e7260..7cfa8e0ce2a 100644
> --- a/board/qualcomm/default.env
> +++ b/board/qualcomm/default.env
> @@ -1,7 +1,7 @@
>  stdin=serial,button-kbd
>  stdout=serial,vidconsole
>  stderr=serial,vidconsole
> -preboot=scsi scan; usb start
> +preboot=usb start
>  fastboot=fastboot -l $fastboot_addr_r usb 0
>  do_boot=bootefi bootmgr
>  bootmenu_0=Boot first available device=run do_boot
> -- 
> 2.34.1
> 

Re: [PATCH v1 1/3] clk: qcom: Add QCS615 SDCC clock support and RPMH-CLK compatibility

[Casey Connolly]

Hi Balaji,

On 26/01/2026 16:59, Balaji Selvanathan wrote:
> Add SDCC (SD Card Controller) clock support for QCS615 platform to
> enable eMMC functionality. This includes adding SDCC1 and SDCC2 clock
> gates, implementing SDCC1 apps clock rate configuration
> and adding QCS615 RPMH clock compatibility to the stub
> driver to handle device tree clock controller references.

For the sake of clarity, could you split the clk-stub patch out to it's
own patch.

> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

> ---
>  drivers/clk/clk-stub.c          |  2 +-
>  drivers/clk/qcom/clock-qcom.h   |  1 +
>  drivers/clk/qcom/clock-qcs615.c | 10 ++++++++++
>  3 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index 117266ac778..1bc749e47b3 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = {
>  
>  static const struct udevice_id stub_clk_ids[] = {
>  	{ .compatible = "qcom,rpmcc" },
> +	{ .compatible = "qcom,qcs615-rpmh-clk" },
>  	{ .compatible = "qcom,sdm670-rpmh-clk" },
>  	{ .compatible = "qcom,sdm845-rpmh-clk" },
>  	{ .compatible = "qcom,sc7180-rpmh-clk" },
> @@ -69,4 +70,3 @@ U_BOOT_DRIVER(clk_stub) = {
>  	.of_match = stub_clk_ids,
>  	.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
>  };
> -
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 3a4550d8536..bc7e0453cba 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -14,6 +14,7 @@
>  #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
>  #define CFG_CLK_SRC_GPLL2 (2 << 8)
>  #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)
> +#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8)
>  #define CFG_CLK_SRC_GPLL9 (2 << 8)
>  #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
>  #define CFG_CLK_SRC_GPLL6 (4 << 8)
> diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
> index 4700baba8c9..483642531ef 100644
> --- a/drivers/clk/qcom/clock-qcs615.c
> +++ b/drivers/clk/qcom/clock-qcs615.c
> @@ -18,6 +18,7 @@
>  #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR	0xf034
>  #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0xf01c
>  #define USB3_PRIM_PHY_AUX_CMD_RCGR		0xf060
> +#define SDCC1_APPS_CLK_CMD_RCGR			0x12028
>  
>  #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
>  #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
> @@ -52,6 +53,10 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
>  				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
>  		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
>  		return rate;
> +	case GCC_SDCC1_APPS_CLK:
> +		clk_rcg_set_rate(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
> +				 1, CFG_CLK_SRC_GPLL6_OUT_MAIN);
> +		return rate;
>  	default:
>  		return 0;
>  	}
> @@ -66,6 +71,11 @@ static const struct gate_clk qcs615_clks[] = {
>  	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
>  	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),

-- 
// Casey (she/her)

Re: [PATCH v1 3/3] board: qualcomm: Remove SCSI scan from default preboot environment

[Casey Connolly]

Hi Balaji,

On 26/01/2026 16:59, Balaji Selvanathan wrote:
> Remove "scsi scan" from the preboot command sequence in the default
> Qualcomm board environment. The SCSI scan command fails on eMMC-based
> boot configurations, causing unnecessary boot delays and potential
> error messages during the preboot phase.

I'm fine with this change in principle, since we already do the
scsi_scan() in qcom_configure_capsule_updates(). However currently this
only happens on Qualcomm boards if EFI_HAVE_CAPSULE_UPDATE is enabled.

Could you move the scsi_scan() call from there to board_late_init()? It
would be even better to introduce a config option for this and do it in
board_r.c similarly to mmc init (perhaps rename initr_mmc to
initr_storage), maybe something for the todo list?

> 
> This change improves boot reliability on platforms using eMMC storage
> as the primary boot device.
It isn't clear from the commit message here but do I understand
correctly that you're booting on a board that can either have eMMC or
UFS storage, and that the UFS controller is enabled in DT despite the
hardware not being present?

I would propose (in addition to the above) that you resolve this with a
runtime DT fixup, I believe SMEM (or maybe the sbl1 shared data
structure?) contain a property describing what storage device we're
booting from, so the other one can be disabled.

Kind regards,

> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  board/qualcomm/default.env | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/qualcomm/default.env b/board/qualcomm/default.env
> index dbf6f4e7260..7cfa8e0ce2a 100644
> --- a/board/qualcomm/default.env
> +++ b/board/qualcomm/default.env
> @@ -1,7 +1,7 @@
>  stdin=serial,button-kbd
>  stdout=serial,vidconsole
>  stderr=serial,vidconsole
> -preboot=scsi scan; usb start
> +preboot=usb start
>  fastboot=fastboot -l $fastboot_addr_r usb 0
>  do_boot=bootefi bootmgr
>  bootmenu_0=Boot first available device=run do_boot

-- 
// Casey (she/her)