* [PATCH 00/12] imx: add i.MX952 support
@ 2026-02-05 13:55 alice.guo
2026-02-05 13:55 ` [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API alice.guo
` (11 more replies)
0 siblings, 12 replies; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
CI: https://github.com/u-boot/u-boot/pull/863/checks
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
Alice Guo (8):
arm: imx: Add i.MX952 CPU type support
imx: ele_ahab: Add i.MX952 support to display_life_cycle()
imx: container: Add i.MX952 support to get_imageset_end()
arm: imx952: Add watchdog base address definitions
arm: imx9: Add i.MX952 SoC support
cpu: imx952: Add i.MX952 support
dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux
arm: dts: Add U-Boot device tree for i.MX952 EVK
Peng Fan (1):
board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support
Ye Li (3):
imx9: scmi: Get DDR size through SM SCMI API
imx95/imx94: Remove board_phys_sdram_size from each board
pinctrl: nxp: Add i.MX952 support
arch/arm/dts/imx952-evk-u-boot.dtsi | 58 +
arch/arm/dts/imx952-u-boot.dtsi | 327 ++++++
arch/arm/include/asm/arch-imx/cpu.h | 1 +
arch/arm/include/asm/arch-imx9/imx-regs.h | 6 +
arch/arm/include/asm/mach-imx/sys_proto.h | 11 +
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/ele_ahab.c | 2 +-
arch/arm/mach-imx/image-container.c | 4 +-
arch/arm/mach-imx/imx9/Kconfig | 23 +
arch/arm/mach-imx/imx9/scmi/common.h | 10 +
arch/arm/mach-imx/imx9/scmi/soc.c | 78 +-
board/nxp/imx94_evk/imx94_evk.c | 7 -
board/nxp/imx952_evk/Kconfig | 12 +
board/nxp/imx952_evk/MAINTAINERS | 6 +
board/nxp/imx952_evk/Makefile | 14 +
board/nxp/imx952_evk/imx952_evk.c | 297 +++++
board/nxp/imx952_evk/imx952_evk.env | 137 +++
board/nxp/imx952_evk/spl.c | 115 ++
board/nxp/imx95_evk/imx95_evk.c | 7 -
configs/imx952_evk_defconfig | 178 +++
doc/board/nxp/imx952_evk.rst | 112 ++
doc/board/nxp/index.rst | 1 +
drivers/cpu/imx8_cpu.c | 2 +
drivers/pinctrl/nxp/pinctrl-imx-scmi.c | 6 +-
dts/upstream/src/arm64/freescale/imx952-clock.h | 215 ++++
dts/upstream/src/arm64/freescale/imx952-evk.dts | 596 ++++++++++
dts/upstream/src/arm64/freescale/imx952-pinfunc.h | 867 ++++++++++++++
dts/upstream/src/arm64/freescale/imx952-power.h | 44 +
dts/upstream/src/arm64/freescale/imx952.dtsi | 1266 +++++++++++++++++++++
include/configs/imx952_evk.h | 31 +
include/scmi_protocols.h | 3 +-
31 files changed, 4404 insertions(+), 34 deletions(-)
---
base-commit: b5213bbfdcb1812be510427857827ee8becb9f8f
change-id: 20260205-imx952-dc74666fd4ab
Best regards,
--
Alice Guo <alice.guo@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:34 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 02/12] imx95/imx94: Remove board_phys_sdram_size from each board alice.guo
` (10 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Ye Li <ye.li@nxp.com>
SM has implemented MISC protocol for get DDR info. Using this API, u-boot
could get DDR size instead of static configs. This will facilitate the DDR
ECC enabled case which has 1/8 DDR size reserved by ECC data. SM get DDR info
API provides the reduced DDR size.
To be compatible with old SM, if calling this API failed, will fall back
to static configs.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/include/asm/mach-imx/sys_proto.h | 10 ++++
arch/arm/mach-imx/imx9/scmi/soc.c | 76 +++++++++++++++++++++++++------
include/scmi_protocols.h | 3 +-
3 files changed, 74 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 46da7a1eff5..6c8bd6c9085 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -254,6 +254,16 @@ struct scmi_rom_passover_get_out {
u32 passover[(sizeof(rom_passover_t) + 8) / 4];
};
+struct scmi_ddr_info_out {
+ s32 status;
+ u32 attributes;
+ u32 mts;
+ u32 startlow;
+ u32 starthigh;
+ u32 endlow;
+ u32 endhigh;
+};
+
#endif
/* For i.MX ULP */
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index c1458ccca3c..e573736825c 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -58,6 +58,35 @@ uint32_t scmi_get_rom_data(rom_passover_t *rom_data)
return 0;
}
+int scmi_misc_ddrinfo(u32 ddrc_id, struct scmi_ddr_info_out *out)
+{
+ u32 in = ddrc_id;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC,
+ .message_id = SCMI_MISC_DDR_INFO_GET,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)out,
+ .out_msg_sz = sizeof(*out),
+ };
+ int ret;
+ struct udevice *dev;
+
+ memset(out, 0, sizeof(*out));
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret != 0 || out->status != 0) {
+ printf("Failed to get ddr cfg, scmi_err = %d\n",
+ out->status);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
#if IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
__weak int board_mmc_get_env_dev(int devno)
{
@@ -335,25 +364,44 @@ void enable_caches(void)
__weak int board_phys_sdram_size(phys_size_t *size)
{
+ struct scmi_ddr_info_out ddr_info;
+ int ret;
+ u32 ddrc_id = 0, ddrc_num = 1;
phys_size_t start, end;
- phys_size_t val;
if (!size)
return -EINVAL;
- val = readl(REG_DDR_CS0_BNDS);
- start = (val >> 16) << 24;
- end = (val & 0xFFFF);
- end = end ? end + 1 : 0;
- end = end << 24;
- *size = end - start;
-
- val = readl(REG_DDR_CS1_BNDS);
- start = (val >> 16) << 24;
- end = (val & 0xFFFF);
- end = end ? end + 1 : 0;
- end = end << 24;
- *size += end - start;
+ *size = 0;
+ do {
+ ret = scmi_misc_ddrinfo(ddrc_id++, &ddr_info);
+ if (ret) {
+ /* if get DDR info failed, fall to default config */
+ *size = PHYS_SDRAM_SIZE;
+#ifdef PHYS_SDRAM_2_SIZE
+ *size += PHYS_SDRAM_2_SIZE;
+#endif
+ return 0;
+ } else {
+ ddrc_num = ((ddr_info.attributes >> 16) & 0x3);
+ start = ddr_info.starthigh;
+ start <<= 32;
+ start += ddr_info.startlow;
+
+ end = ddr_info.endhigh;
+ end <<= 32;
+ end += ddr_info.endlow;
+
+ *size += end + 1 - start;
+
+ debug("ddr info attr 0x%x, start 0x%x 0x%x, end 0x%x 0x%x, mts %u\n",
+ ddr_info.attributes, ddr_info.starthigh, ddr_info.startlow,
+ ddr_info.endhigh, ddr_info.endlow, ddr_info.mts);
+ }
+ } while (ddrc_id < ddrc_num);
+
+ /* SM reports total DDR size, need remove secure memory */
+ *size -= PHYS_SDRAM - 0x80000000;
return 0;
}
diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index ecab021b472..555ffa0a61b 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -54,7 +54,8 @@ enum scmi_discovery_id {
};
enum scmi_imx_misc_message_id {
- SCMI_MISC_ROM_PASSOVER_GET = 0x7
+ SCMI_MISC_ROM_PASSOVER_GET = 0x7,
+ SCMI_MISC_DDR_INFO_GET = 0x22,
};
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 02/12] imx95/imx94: Remove board_phys_sdram_size from each board
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
2026-02-05 13:55 ` [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:35 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 03/12] pinctrl: nxp: Add i.MX952 support alice.guo
` (9 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Ye Li <ye.li@nxp.com>
Change to use default board_phys_sdram_size implementation in soc.c,
which will call SM API to get DDR size.
If board has special implementation for DDR size, then board_phys_sdram_size
could be implemented in board file to override the default one in soc.c.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
board/nxp/imx94_evk/imx94_evk.c | 7 -------
board/nxp/imx95_evk/imx95_evk.c | 7 -------
2 files changed, 14 deletions(-)
diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c
index 588aa7548d4..a4b59bb7cea 100644
--- a/board/nxp/imx94_evk/imx94_evk.c
+++ b/board/nxp/imx94_evk/imx94_evk.c
@@ -32,10 +32,3 @@ int board_late_init(void)
return 0;
}
-
-int board_phys_sdram_size(phys_size_t *size)
-{
- *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c
index ca1d916deab..74a6c14bf6d 100644
--- a/board/nxp/imx95_evk/imx95_evk.c
+++ b/board/nxp/imx95_evk/imx95_evk.c
@@ -22,10 +22,3 @@ int board_late_init(void)
return 0;
}
-
-int board_phys_sdram_size(phys_size_t *size)
-{
- *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 03/12] pinctrl: nxp: Add i.MX952 support
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
2026-02-05 13:55 ` [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API alice.guo
2026-02-05 13:55 ` [PATCH v1 02/12] imx95/imx94: Remove board_phys_sdram_size from each board alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:36 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 04/12] arm: imx: Add i.MX952 CPU type support alice.guo
` (8 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Ye Li <ye.li@nxp.com>
Multiple pads can drive the same module input pin, and a daisy chain
register is used to select the active input path. This patch defines
DAISY_OFFSET_IMX952 (0x460) and allows binding on i.MX952.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
drivers/pinctrl/nxp/pinctrl-imx-scmi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
index 781835c6852..3cc2b85e151 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
@@ -17,6 +17,7 @@
#define DAISY_OFFSET_IMX95 0x408
#define DAISY_OFFSET_IMX94 0x608
+#define DAISY_OFFSET_IMX952 0x460
/* SCMI pin control types */
#define PINCTRL_TYPE_MUX 192
@@ -136,6 +137,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev)
priv->daisy_offset = DAISY_OFFSET_IMX95;
else if (IS_ENABLED(CONFIG_IMX94))
priv->daisy_offset = DAISY_OFFSET_IMX94;
+ else if (IS_ENABLED(CONFIG_IMX952))
+ priv->daisy_offset = DAISY_OFFSET_IMX952;
else
return -EINVAL;
@@ -144,7 +147,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev)
static int imx_scmi_pinctrl_bind(struct udevice *dev)
{
- if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94))
+ if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) ||
+ IS_ENABLED(CONFIG_IMX952))
return 0;
return -ENODEV;
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 04/12] arm: imx: Add i.MX952 CPU type support
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (2 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 03/12] pinctrl: nxp: Add i.MX952 support alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:37 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 05/12] imx: ele_ahab: Add i.MX952 support to display_life_cycle() alice.guo
` (7 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Add CPU type definition and detection macro for i.MX952 SoC.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/include/asm/arch-imx/cpu.h | 1 +
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 1af9778f8ce..25d0f205fde 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -79,6 +79,7 @@
#define MXC_CPU_IMX95 0x1C1 /* dummy ID */
#define MXC_CPU_IMX94 0x1C2 /* dummy ID */
+#define MXC_CPU_IMX952 0x1C3 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 6c8bd6c9085..e2076fb676d 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -99,6 +99,7 @@ struct bd_info;
#define is_imx94() (is_cpu_type(MXC_CPU_IMX94))
#define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
+#define is_imx952() (is_cpu_type(MXC_CPU_IMX952))
#define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
#define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 05/12] imx: ele_ahab: Add i.MX952 support to display_life_cycle()
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (3 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 04/12] arm: imx: Add i.MX952 CPU type support alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:38 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 06/12] imx: container: Add i.MX952 support to get_imageset_end() alice.guo
` (6 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Extend display_life_cycle() to support i.MX952.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/mach-imx/ele_ahab.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 38e671e3935..73869aa5590 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -411,7 +411,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_SUCCESS;
}
-#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94)
+#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) || IS_ENABLED(CONFIG_IMX952)
#define FSB_LC_OFFSET 0x414
#define LC_OEM_OPEN 0x10
static void display_life_cycle(u32 lc)
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 06/12] imx: container: Add i.MX952 support to get_imageset_end()
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (4 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 05/12] imx: ele_ahab: Add i.MX952 support to display_life_cycle() alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:40 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions alice.guo
` (5 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Extend get_imageset_end() to handle i.MX952.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/mach-imx/image-container.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 78f2488cf6d..7bfcc9d7e9d 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type)
debug("seco container size 0x%x\n", value_container[0]);
- if (is_imx95() || is_imx94()) {
+ if (is_imx95() || is_imx94() || is_imx952()) {
offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw);
@@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type)
value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL);
if (value_container[2] < 0) {
debug("Parse scu container image failed %d, only seco container\n", value_container[2]);
- if (is_imx95() || is_imx94())
+ if (is_imx95() || is_imx94() || is_imx952())
return value_container[1] + offset[1]; /* return seco + v2x container total size */
else
return value_container[0] + offset[0]; /* return seco container total size */
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (5 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 06/12] imx: container: Add i.MX952 support to get_imageset_end() alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:41 ` Peng Fan
2026-02-06 3:59 ` Fabio Estevam
2026-02-05 13:55 ` [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support alice.guo
` (4 subsequent siblings)
11 siblings, 2 replies; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Add WDG3, WDG4 and WDG5 base addresses for i.MX952.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 2d084e5227a..7c7a34f74af 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -17,6 +17,11 @@
#define ANATOP_BASE_ADDR 0x44480000UL
+#ifdef CONFIG_IMX952
+#define WDG3_BASE_ADDR 0x420b0000UL
+#define WDG4_BASE_ADDR 0x420c0000UL
+#define WDG5_BASE_ADDR 0x420d0000UL
+#else
#ifdef CONFIG_IMX94
#define WDG3_BASE_ADDR 0x49220000UL
#define WDG4_BASE_ADDR 0x49230000UL
@@ -25,6 +30,7 @@
#define WDG4_BASE_ADDR 0x424a0000UL
#endif
#define WDG5_BASE_ADDR 0x424b0000UL
+#endif
#define GPIO2_BASE_ADDR 0x43810000UL
#define GPIO3_BASE_ADDR 0x43820000UL
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (6 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:45 ` Peng Fan
2026-02-22 1:34 ` David Zang
2026-02-05 13:55 ` [PATCH v1 09/12] cpu: imx952: Add i.MX952 support alice.guo
` (3 subsequent siblings)
11 siblings, 2 replies; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Add basic SoC support for i.MX952:
- Add CONFIG_IMX952 Kconfig option
- Include i.MX952 clock and power headers
- Set CPU speed grade to 1.7GHz for i.MX952
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/mach-imx/imx9/Kconfig | 9 +++++++++
arch/arm/mach-imx/imx9/scmi/common.h | 10 ++++++++++
arch/arm/mach-imx/imx9/scmi/soc.c | 2 ++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index d9f97e4328c..716940930a6 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -47,6 +47,15 @@ config IMX94
select SCMI_FIRMWARE
select SPL_IMX_CONTAINER_USE_TRAMPOLINE
+config IMX952
+ bool
+ select ARMV8_SPL_EXCEPTION_VECTORS
+ select DM_MAILBOX
+ select IMX9
+ select IMX_PQC_SUPPORT
+ select SCMI_FIRMWARE
+ select SPL_IMX_CONTAINER_USE_TRAMPOLINE
+
config SYS_SOC
default "imx9"
diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h
index dd4675402c7..c3610127dce 100644
--- a/arch/arm/mach-imx/imx9/scmi/common.h
+++ b/arch/arm/mach-imx/imx9/scmi/common.h
@@ -21,6 +21,16 @@
#define IMX95_PD_M70 IMX95_PD_M7
#endif
+#ifdef CONFIG_IMX952
+#define IMX_PLAT 952
+#include <imx952-clock.h>
+#include <imx952-power.h>
+
+#define IMX952_CLK_SEL_A55C0 IMX952_CLK_GPR_SEL_A55C0
+#define IMX952_PD_M70 IMX952_PD_M7
+#define IMX952_CLK_FLEXSPI1 IMX952_CLK_XSPI1
+#define IMX952_CLK_24M IMX952_CLK_OSC24M
+#endif
#define IMX_PLAT_STR__(plat) # plat
#define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT)
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index e573736825c..f0443ccfb2d 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -154,6 +154,8 @@ u32 get_cpu_speed_grade_hz(void)
if (is_imx95())
max_speed = 2000000000;
+ if (is_imx952())
+ max_speed = 1700000000;
/* In case the fuse of speed grade not programmed */
if (speed > max_speed)
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 09/12] cpu: imx952: Add i.MX952 support
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (7 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:46 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux alice.guo
` (2 subsequent siblings)
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
This patch is used to add the imx type string of i.MX952 ao that the
i.MX952 CPU info can be printed.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
drivers/cpu/imx8_cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 5f17122c36c..1c78f882775 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -115,6 +115,8 @@ static const char *get_imx_type_str(u32 imxtype)
return "95";
case MXC_CPU_IMX94:
return "94";
+ case MXC_CPU_IMX952:
+ return "952";
default:
return "??";
}
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (8 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 09/12] cpu: imx952: Add i.MX952 support alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-05 15:38 ` Tom Rini
2026-02-05 13:55 ` [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK alice.guo
2026-02-05 13:55 ` [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support alice.guo
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Sync i.MX952 device tree files from linux-next next-20260202:
- Add imx952.dtsi for SoC
- Add imx952-evk.dts for i.MX952 EVK board
- Add imx952-*.h headers for clock, pinctrl and power
Imported from linux-next commit 193579fe0138 ("Add linux-next specific
ifiles for 20260202")
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
dts/upstream/src/arm64/freescale/imx952-clock.h | 215 ++++
dts/upstream/src/arm64/freescale/imx952-evk.dts | 596 ++++++++++
dts/upstream/src/arm64/freescale/imx952-pinfunc.h | 867 ++++++++++++++
dts/upstream/src/arm64/freescale/imx952-power.h | 44 +
dts/upstream/src/arm64/freescale/imx952.dtsi | 1266 +++++++++++++++++++++
5 files changed, 2988 insertions(+)
diff --git a/dts/upstream/src/arm64/freescale/imx952-clock.h b/dts/upstream/src/arm64/freescale/imx952-clock.h
new file mode 100644
index 00000000000..7d6f6635dc0
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx952-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __CLOCK_IMX952_H__
+#define __CLOCK_IMX952_H__
+
+/* Clock Source */
+#define IMX952_CLK_EXT 0
+#define IMX952_CLK_OSC32K 1
+#define IMX952_CLK_OSC24M 2
+#define IMX952_CLK_FRO 3
+#define IMX952_CLK_SYSPLL1_VCO 4
+#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5
+#define IMX952_CLK_SYSPLL1_PFD0 6
+#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7
+#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8
+#define IMX952_CLK_SYSPLL1_PFD1 9
+#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10
+#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11
+#define IMX952_CLK_SYSPLL1_PFD2 12
+#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13
+#define IMX952_CLK_AUDIOPLL1_VCO 14
+#define IMX952_CLK_AUDIOPLL1 15
+#define IMX952_CLK_AUDIOPLL2_VCO 16
+#define IMX952_CLK_AUDIOPLL2 17
+#define IMX952_CLK_VIDEOPLL1_VCO 18
+#define IMX952_CLK_VIDEOPLL1 19
+#define IMX952_CLK_SRC_RESERVED20 20
+#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21
+#define IMX952_CLK_SYSPLL1_PFD3 22
+#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23
+#define IMX952_CLK_ARMPLL_VCO 24
+#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25
+#define IMX952_CLK_ARMPLL_PFD0 26
+#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27
+#define IMX952_CLK_ARMPLL_PFD1 28
+#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29
+#define IMX952_CLK_ARMPLL_PFD2 30
+#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31
+#define IMX952_CLK_ARMPLL_PFD3 32
+#define IMX952_CLK_DRAMPLL_VCO 33
+#define IMX952_CLK_DRAMPLL 34
+#define IMX952_CLK_HSIOPLL_VCO 35
+#define IMX952_CLK_HSIOPLL 36
+#define IMX952_CLK_LDBPLL_VCO 37
+#define IMX952_CLK_LDBPLL 38
+#define IMX952_CLK_EXT1 39
+#define IMX952_CLK_EXT2 40
+
+/* Clock ROOT */
+#define IMX952_CLK_ADC 41
+#define IMX952_CLK_RESERVED1 42
+#define IMX952_CLK_BUSAON 43
+#define IMX952_CLK_CAN1 44
+#define IMX952_CLK_RESERVED4 45
+#define IMX952_CLK_I3C1SLOW 46
+#define IMX952_CLK_LPI2C1 47
+#define IMX952_CLK_LPI2C2 48
+#define IMX952_CLK_LPSPI1 49
+#define IMX952_CLK_LPSPI2 50
+#define IMX952_CLK_LPTMR1 51
+#define IMX952_CLK_LPUART1 52
+#define IMX952_CLK_LPUART2 53
+#define IMX952_CLK_M33 54
+#define IMX952_CLK_M33SYSTICK 55
+#define IMX952_CLK_RESERVED15 56
+#define IMX952_CLK_PDM 57
+#define IMX952_CLK_SAI1 58
+#define IMX952_CLK_RESERVED18 59
+#define IMX952_CLK_TPM2 60
+#define IMX952_CLK_RESERVED20 61
+#define IMX952_CLK_CAMAPB 62
+#define IMX952_CLK_CAMAXI 63
+#define IMX952_CLK_CAMCM0 64
+#define IMX952_CLK_CAMISI 65
+#define IMX952_CLK_CAMPHYCFG 66
+#define IMX952_CLK_MIPIPHYPLLBYPASS 67
+#define IMX952_CLK_RESERVED27 68
+#define IMX952_CLK_MIPITESTBYTE 69
+#define IMX952_CLK_A55 70
+#define IMX952_CLK_A55MTRBUS 71
+#define IMX952_CLK_A55PERIPH 72
+#define IMX952_CLK_DRAMALT 73
+#define IMX952_CLK_DRAMAPB 74
+#define IMX952_CLK_DISPAPB 75
+#define IMX952_CLK_DISPAXI 76
+#define IMX952_CLK_DISPLPSPI 77
+#define IMX952_CLK_DISPOCRAM 78
+#define IMX952_CLK_DISPPHYCFG 79
+#define IMX952_CLK_DISP1PIX 80
+#define IMX952_CLK_DISPCDPHYAPB 81
+#define IMX952_CLK_RESERVED41 82
+#define IMX952_CLK_GPUAPB 83
+#define IMX952_CLK_GPU 84
+#define IMX952_CLK_HSIOACSCAN480M 85
+#define IMX952_CLK_HSIOACSCAN80M 86
+#define IMX952_CLK_HSIO 87
+#define IMX952_CLK_HSIOPCIEAUX 88
+#define IMX952_CLK_HSIOPCIETEST160M 89
+#define IMX952_CLK_HSIOPCIETEST400M 90
+#define IMX952_CLK_HSIOPCIETEST500M 91
+#define IMX952_CLK_HSIOUSBTEST50M 92
+#define IMX952_CLK_HSIOUSBTEST60M 93
+#define IMX952_CLK_BUSM7 94
+#define IMX952_CLK_M7 95
+#define IMX952_CLK_M7SYSTICK 96
+#define IMX952_CLK_BUSNETCMIX 97
+#define IMX952_CLK_ENET 98
+#define IMX952_CLK_ENETPHYTEST200M 99
+#define IMX952_CLK_ENETPHYTEST500M 100
+#define IMX952_CLK_ENETPHYTEST667M 101
+#define IMX952_CLK_ENETREF 102
+#define IMX952_CLK_ENETTIMER1 103
+#define IMX952_CLK_RESERVED63 104
+#define IMX952_CLK_SAI2 105
+#define IMX952_CLK_NOCAPB 106
+#define IMX952_CLK_NOC 107
+#define IMX952_CLK_NPUAPB 108
+#define IMX952_CLK_NPU 109
+#define IMX952_CLK_CCMCKO1 110
+#define IMX952_CLK_CCMCKO2 111
+#define IMX952_CLK_CCMCKO3 112
+#define IMX952_CLK_CCMCKO4 113
+#define IMX952_CLK_VPUAPB 114
+#define IMX952_CLK_VPU 115
+#define IMX952_CLK_RESERVED75 116
+#define IMX952_CLK_RESERVED76 117
+#define IMX952_CLK_AUDIOXCVR 118
+#define IMX952_CLK_BUSWAKEUP 119
+#define IMX952_CLK_CAN2 120
+#define IMX952_CLK_CAN3 121
+#define IMX952_CLK_CAN4 122
+#define IMX952_CLK_CAN5 123
+#define IMX952_CLK_FLEXIO1 124
+#define IMX952_CLK_FLEXIO2 125
+#define IMX952_CLK_XSPI1 126
+#define IMX952_CLK_RESERVED86 127
+#define IMX952_CLK_I3C2SLOW 128
+#define IMX952_CLK_LPI2C3 129
+#define IMX952_CLK_LPI2C4 130
+#define IMX952_CLK_LPI2C5 131
+#define IMX952_CLK_LPI2C6 132
+#define IMX952_CLK_LPI2C7 133
+#define IMX952_CLK_LPI2C8 134
+#define IMX952_CLK_LPSPI3 135
+#define IMX952_CLK_LPSPI4 136
+#define IMX952_CLK_LPSPI5 137
+#define IMX952_CLK_LPSPI6 138
+#define IMX952_CLK_LPSPI7 139
+#define IMX952_CLK_LPSPI8 140
+#define IMX952_CLK_LPTMR2 141
+#define IMX952_CLK_LPUART3 142
+#define IMX952_CLK_LPUART4 143
+#define IMX952_CLK_LPUART5 144
+#define IMX952_CLK_LPUART6 145
+#define IMX952_CLK_LPUART7 146
+#define IMX952_CLK_LPUART8 147
+#define IMX952_CLK_SAI3 148
+#define IMX952_CLK_SAI4 149
+#define IMX952_CLK_SAI5 150
+#define IMX952_CLK_SPDIF 151
+#define IMX952_CLK_SWOTRACE 152
+#define IMX952_CLK_TPM4 153
+#define IMX952_CLK_TPM5 154
+#define IMX952_CLK_TPM6 155
+#define IMX952_CLK_MIPIPHYDFT400 156
+#define IMX952_CLK_MIPIPHYDFT540 157
+#define IMX952_CLK_USDHC1 158
+#define IMX952_CLK_USDHC2 159
+#define IMX952_CLK_USDHC3 160
+#define IMX952_CLK_V2XPK 161
+#define IMX952_CLK_WAKEUPAXI 162
+#define IMX952_CLK_XSPISLVROOT 163
+#define IMX952_CLK_AUDMIX1 164
+#define IMX952_CLK_ASRC1 165
+#define IMX952_CLK_ASRC2 166
+#define IMX952_CLK_GPT1 167
+#define IMX952_CLK_GPT2 168
+#define IMX952_CLK_GPT3 169
+#define IMX952_CLK_GPT4 170
+
+/* Clock GPR SEL */
+#define IMX952_CLK_GPR_SEL_EXT 171
+#define IMX952_CLK_GPR_SEL_A55C0 172
+#define IMX952_CLK_GPR_SEL_A55C1 173
+#define IMX952_CLK_GPR_SEL_A55C2 174
+#define IMX952_CLK_GPR_SEL_A55C3 175
+#define IMX952_CLK_GPR_SEL_A55P 176
+#define IMX952_CLK_GPR_SEL_DRAM 177
+#define IMX952_CLK_GPR_SEL_TEMPSENSE 178
+
+/* Clock CGC */
+#define IMX952_CLK_CGC_NPU 179
+#define IMX952_CLK_CGC_GPU 180
+#define IMX952_CLK_CGC_CAMISI 181
+#define IMX952_CLK_CGC_CAMISP 182
+#define IMX952_CLK_CGC_CAMCSI0 183
+#define IMX952_CLK_CGC_CAMCSI1 184
+#define IMX952_CLK_CGC_CAMOCRAM 185
+#define IMX952_CLK_CGC_HSIOUSB 186
+#define IMX952_CLK_CGC_HSIOPCIE 187
+#define IMX952_CLK_CGC_DISPOCRAM 188
+#define IMX952_CLK_CGC_DISPSEERIS 189
+#define IMX952_CLK_CGC_DISPDSI 190
+#define IMX952_CLK_CGC_NOCGIC 191
+#define IMX952_CLK_CGC_NOCOCRAM 192
+#define IMX952_CLK_CGC_NETC 193
+#define IMX952_CLK_CGC_VPUENC 194
+#define IMX952_CLK_CGC_VPUJPEGENC 195
+#define IMX952_CLK_CGC_VPUJPEGDEC 196
+#define IMX952_CLK_CGC_VPUDEC 197
+
+#endif
diff --git a/dts/upstream/src/arm64/freescale/imx952-evk.dts b/dts/upstream/src/arm64/freescale/imx952-evk.dts
new file mode 100644
index 00000000000..b838323468d
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx952-evk.dts
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx952.dtsi"
+
+#define FALLING_EDGE BIT(0)
+#define RISING_EDGE BIT(1)
+
+#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */
+#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */
+#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */
+#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */
+#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */
+
+/ {
+ model = "NXP i.MX952 EVK board";
+ compatible = "fsl,imx952-evk", "fsl,imx952";
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ i2c6 = &lpi2c7;
+ i2c7 = &lpi2c8;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ spi6 = &lpspi7;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>;
+ cooling-levels = <64 128 192 255>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ flexcan1_phy: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+ enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>;
+ };
+
+ flexcan2_phy: can-phy1 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+ enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_SW";
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SW";
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VDD_SD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <12000>;
+ };
+
+ reg_usb_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+};
+
+/* pin conflict with PDM */
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ phys = <&flexcan1_phy>;
+ status = "disabled";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ phys = <&flexcan2_phy>;
+ status = "okay";
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ adp5585: io-expander@34 {
+ compatible = "adi,adp5585-00", "adi,adp5585";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-reserved-ranges = <5 1>;
+ #pwm-cells = <3>;
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ i2c3_pcal6408: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_3p3v>;
+ };
+};
+
+&lpi2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c4>;
+ status = "okay";
+
+ i2c4_pcal6408: gpio@21 {
+ compatible = "nxp,pcal6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_pcal6408>;
+ vcc-supply = <®_3p3v>;
+ };
+};
+
+&lpi2c6 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c6>;
+ status = "okay";
+
+ pcal6416: gpio@21 {
+ compatible = "nxp,pcal6416";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x21>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6416>;
+ vcc-supply = <®_3p3v>;
+
+ pdm-can-sel-hog {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ mqs-en-hog {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+};
+
+&lpi2c7 {
+ clock-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c7>;
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ptn5110>;
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <0>;
+ self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&lpuart1 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart5 {
+ /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&lpspi7 {
+ cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi7>;
+ status = "okay";
+};
+
+&scmi_misc {
+ nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1
+ BRD_SM_CTRL_M2E_WAKE 1
+ BRD_SM_CTRL_BT_WAKE 1
+ BRD_SM_CTRL_M2M_WAKE 1
+ BRD_SM_CTRL_BUTTON 1>;
+};
+
+&tpm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm3>;
+ status = "okay";
+};
+
+&tpm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm6>;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usb2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
+ IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e
+ IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
+ IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c4: lpi2c4grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_i2c4_pcal6408: i2c4pcal6408grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c6: lpi2c6grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c7: lpi2c7grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpspi7: lpspi7grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e
+ IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e
+ IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e
+ IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e
+ >;
+ };
+
+ pinctrl_pcal6416: pcal6416grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e
+ >;
+ };
+
+ pinctrl_ptn5110: ptn5110grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e
+ >;
+ };
+
+ pinctrl_tpm3: tpm3grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e
+ >;
+ };
+
+ pinctrl_tpm6: tpm6grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
+ IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e
+ IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e
+ IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e
+ IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e
+ IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e
+ IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e
+ IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e
+ IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e
+ IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e
+ IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e
+ IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e
+ IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e
+ IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e
+ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e
+ IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e
+ IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e
+ IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e
+ IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e
+ IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e
+ IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e
+ IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e
+ IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e
+ IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e
+ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e
+ IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e
+ IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e
+ IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e
+ IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e
+ IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e
+ IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e
+ IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e
+ IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e
+ IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e
+ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
+ IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
+ IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
+ IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
+ IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
+ IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
+ IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
+ IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
+ IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
+ IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
+ IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
+ IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
+ IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
+ IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
+ IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
+ IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
+ IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
+ IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
+ IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx952-pinfunc.h b/dts/upstream/src/arm64/freescale/imx952-pinfunc.h
new file mode 100644
index 00000000000..debe6ede2d7
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx952-pinfunc.h
@@ -0,0 +1,867 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DTS_IMX952_PINFUNC_H__
+#define __DTS_IMX952_PINFUNC_H__
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_TDI 0x0000 0x0230 0x05FC 0x00 0x00
+#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0230 0x0000 0x01 0x00
+#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0230 0x0000 0x02 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_CAN2_TX 0x0000 0x0230 0x0000 0x03 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_30 0x0000 0x0230 0x0000 0x04 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_GPIO3_IO_28 0x0000 0x0230 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x0000 0x0230 0x059C 0x06 0x00
+
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_TMS 0x0004 0x0234 0x0600 0x00 0x00
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_31 0x0004 0x0234 0x0000 0x04 0x00
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_GPIO3_IO_29 0x0004 0x0234 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x0004 0x0234 0x0000 0x06 0x00
+
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_TCK 0x0008 0x0238 0x05F8 0x00 0x00
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0008 0x0238 0x04B4 0x04 0x00
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_GPIO3_IO_30 0x0008 0x0238 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0008 0x0238 0x0598 0x06 0x00
+
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_TDO 0x000C 0x023C 0x0000 0x00 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x023C 0x0000 0x01 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM2 0x000C 0x023C 0x0000 0x02 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_CAN2_RX 0x000C 0x023C 0x04A4 0x03 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x000C 0x023C 0x04B8 0x04 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_GPIO3_IO_31 0x000C 0x023C 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x000C 0x023C 0x05A0 0x06 0x00
+
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPIO2_IO_0 0x0010 0x0240 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x0010 0x0240 0x0530 0x01 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPTMUX_INOUT0 0x0010 0x0240 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPSPI6_PCS0 0x0010 0x0240 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPUART5_TX 0x0010 0x0240 0x05A0 0x05 0x01
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C5_SDA 0x0010 0x0240 0x0540 0x06 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x0010 0x0240 0x04BC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPIO2_IO_1 0x0014 0x0244 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x0014 0x0244 0x052C 0x01 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPTMUX_INOUT1 0x0014 0x0244 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPSPI6_SIN 0x0014 0x0244 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPUART5_RX 0x0014 0x0244 0x059C 0x05 0x01
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C5_SCL 0x0014 0x0244 0x053C 0x06 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x0014 0x0244 0x04C0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPIO2_IO_2 0x0018 0x0248 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C4_SDA 0x0018 0x0248 0x0538 0x01 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPTMUX_INOUT2 0x0018 0x0248 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPSPI6_SOUT 0x0018 0x0248 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0018 0x0248 0x0598 0x05 0x01
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x0018 0x0248 0x0548 0x06 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x0018 0x0248 0x04C4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPIO2_IO_3 0x001C 0x024C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C4_SCL 0x001C 0x024C 0x0534 0x01 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPTMUX_INOUT3 0x001C 0x024C 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPSPI6_SCK 0x001C 0x024C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPUART5_RTS_B 0x001C 0x024C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x001C 0x024C 0x0544 0x06 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x001C 0x024C 0x04C8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x0020 0x0250 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x0020 0x0250 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0250 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPTMUX_INOUT4 0x0020 0x0250 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPSPI7_PCS0 0x0020 0x0250 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPUART6_TX 0x0020 0x0250 0x05AC 0x05 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPI2C6_SDA 0x0020 0x0250 0x0548 0x06 0x01
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x0020 0x0250 0x04CC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPIO2_IO_5 0x0024 0x0254 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_TPM4_CH0 0x0024 0x0254 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_0 0x0024 0x0254 0x0464 0x02 0x01
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPTMUX_INOUT5 0x0024 0x0254 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x0024 0x0254 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPUART6_RX 0x0024 0x0254 0x05A8 0x05 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPI2C6_SCL 0x0024 0x0254 0x0544 0x06 0x01
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x0024 0x0254 0x04D0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPIO2_IO_6 0x0028 0x0258 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_TPM5_CH0 0x0028 0x0258 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_1 0x0028 0x0258 0x0468 0x02 0x01
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPTMUX_INOUT6 0x0028 0x0258 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x0028 0x0258 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0028 0x0258 0x05A4 0x05 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPI2C7_SDA 0x0028 0x0258 0x0550 0x06 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x0028 0x0258 0x04D4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPIO2_IO_7 0x002C 0x025C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI3_PCS1 0x002C 0x025C 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPTMUX_INOUT7 0x002C 0x025C 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x002C 0x025C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPUART6_RTS_B 0x002C 0x025C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPI2C7_SCL 0x002C 0x025C 0x054C 0x06 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x002C 0x025C 0x04D8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x0030 0x0260 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPSPI3_PCS0 0x0030 0x0260 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPTMUX_INOUT8 0x0030 0x0260 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_TPM6_CH0 0x0030 0x0260 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPUART7_TX 0x0030 0x0260 0x05B4 0x05 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x0030 0x0260 0x0550 0x06 0x01
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0030 0x0260 0x04DC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPIO2_IO_9 0x0034 0x0264 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x0034 0x0264 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPTMUX_INOUT9 0x0034 0x0264 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_TPM3_EXTCLK 0x0034 0x0264 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPUART7_RX 0x0034 0x0264 0x05B0 0x05 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x0034 0x0264 0x054C 0x06 0x01
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0034 0x0264 0x04E0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x0038 0x0268 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x0038 0x0268 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPTMUX_INOUT10 0x0038 0x0268 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_TPM4_EXTCLK 0x0038 0x0268 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPUART7_CTS_B 0x0038 0x0268 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPI2C8_SDA 0x0038 0x0268 0x0558 0x06 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x0038 0x0268 0x04E4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x003C 0x026C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x003C 0x026C 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPTMUX_INOUT11 0x003C 0x026C 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_TPM5_EXTCLK 0x003C 0x026C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPUART7_RTS_B 0x003C 0x026C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPI2C8_SCL 0x003C 0x026C 0x0554 0x06 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x003C 0x026C 0x04E8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_GPIO2_IO_12 0x0040 0x0270 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x0040 0x0270 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_2 0x0040 0x0270 0x046C 0x02 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0040 0x0270 0x04EC 0x03 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPSPI8_PCS0 0x0040 0x0270 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPUART8_TX 0x0040 0x0270 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPI2C8_SDA 0x0040 0x0270 0x0558 0x06 0x01
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x0040 0x0270 0x05BC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_GPIO2_IO_13 0x0044 0x0274 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x0044 0x0274 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_3 0x0044 0x0274 0x0470 0x02 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPSPI8_SIN 0x0044 0x0274 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPUART8_RX 0x0044 0x0274 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPI2C8_SCL 0x0044 0x0274 0x0554 0x06 0x01
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0044 0x0274 0x04F0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_GPIO2_IO_14 0x0048 0x0278 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART3_TX 0x0048 0x0278 0x0588 0x01 0x01
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPSPI8_SOUT 0x0048 0x0278 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART8_CTS_B 0x0048 0x0278 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART4_TX 0x0048 0x0278 0x0594 0x06 0x01
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x0048 0x0278 0x04F4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_GPIO2_IO_15 0x004C 0x027C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART3_RX 0x004C 0x027C 0x0584 0x01 0x01
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x004C 0x027C 0x0624 0x03 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPSPI8_SCK 0x004C 0x027C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART8_RTS_B 0x004C 0x027C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART4_RX 0x004C 0x027C 0x0590 0x06 0x01
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x004C 0x027C 0x04F8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x0050 0x0280 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x0050 0x0280 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_2 0x0050 0x0280 0x046C 0x02 0x01
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0050 0x0280 0x0580 0x04 0x01
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0050 0x0280 0x0564 0x05 0x00
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART4_CTS_B 0x0050 0x0280 0x058C 0x06 0x01
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0050 0x0280 0x04FC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x0054 0x0284 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x0054 0x0284 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART3_RTS_B 0x0054 0x0284 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0054 0x0284 0x0560 0x05 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART4_RTS_B 0x0054 0x0284 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0054 0x0284 0x0500 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x0058 0x0288 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0058 0x0288 0x05B8 0x01 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI5_PCS0 0x0058 0x0288 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0058 0x0288 0x055C 0x05 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_TPM5_CH2 0x0058 0x0288 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x0058 0x0288 0x0504 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_GPIO2_IO_19 0x005C 0x028C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x005C 0x028C 0x05BC 0x01 0x01
+#define IMX952_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_3 0x005C 0x028C 0x0470 0x02 0x01
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x005C 0x028C 0x0508 0x03 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI5_SIN 0x005C 0x028C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI4_SIN 0x005C 0x028C 0x056C 0x05 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x005C 0x028C 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x005C 0x028C 0x05F4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x0060 0x0290 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x0060 0x0290 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_0 0x0060 0x0290 0x0464 0x02 0x02
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI5_SOUT 0x0060 0x0290 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI4_SOUT 0x0060 0x0290 0x0570 0x05 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_TPM3_CH1 0x0060 0x0290 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0060 0x0290 0x050C 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x0064 0x0294 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x0064 0x0294 0x05F4 0x01 0x01
+#define IMX952_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0294 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0064 0x0294 0x0510 0x03 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI5_SCK 0x0064 0x0294 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI4_SCK 0x0064 0x0294 0x0568 0x05 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_TPM4_CH1 0x0064 0x0294 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0064 0x0294 0x05B8 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_GPIO2_IO_22 0x0068 0x0298 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_USDHC3_CLK 0x0068 0x0298 0x0604 0x01 0x00
+#define IMX952_PAD_GPIO_IO22__HSIOMIX_TOP_USB1_OTG_OC 0x0068 0x0298 0x047C 0x03 0x01
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM5_CH1 0x0068 0x0298 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM6_EXTCLK 0x0068 0x0298 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_LPI2C5_SDA 0x0068 0x0298 0x0540 0x06 0x01
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x0068 0x0298 0x0514 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_GPIO2_IO_23 0x006C 0x029C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_USDHC3_CMD 0x006C 0x029C 0x0608 0x01 0x00
+#define IMX952_PAD_GPIO_IO23__HSIOMIX_TOP_USB2_OTG_OC 0x006C 0x029C 0x0480 0x03 0x01
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_TPM6_CH1 0x006C 0x029C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_LPI2C5_SCL 0x006C 0x029C 0x053C 0x06 0x01
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x006C 0x029C 0x0518 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_GPIO2_IO_24 0x0070 0x02A0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_USDHC3_DATA0 0x0070 0x02A0 0x060C 0x01 0x00
+#define IMX952_PAD_GPIO_IO24__HSIOMIX_TOP_USB1_OTG_PWR 0x0070 0x02A0 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TPM3_CH3 0x0070 0x02A0 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TDO 0x0070 0x02A0 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_LPSPI6_PCS1 0x0070 0x02A0 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0070 0x02A0 0x051C 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_GPIO2_IO_25 0x0074 0x02A4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_USDHC3_DATA1 0x0074 0x02A4 0x0610 0x01 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x0074 0x02A4 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO25__HSIOMIX_TOP_USB2_OTG_PWR 0x0074 0x02A4 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TPM4_CH3 0x0074 0x02A4 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TCK 0x0074 0x02A4 0x05F8 0x05 0x01
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_LPSPI7_PCS1 0x0074 0x02A4 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0074 0x02A4 0x0520 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x0078 0x02A8 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_USDHC3_DATA2 0x0078 0x02A8 0x0614 0x01 0x00
+#define IMX952_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_1 0x0078 0x02A8 0x0468 0x02 0x02
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x0078 0x02A8 0x04AC 0x03 0x01
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TPM5_CH3 0x0078 0x02A8 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TDI 0x0078 0x02A8 0x05FC 0x05 0x01
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_LPSPI8_PCS1 0x0078 0x02A8 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x0078 0x02A8 0x0000 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_GPIO2_IO_27 0x007C 0x02AC 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_USDHC3_DATA3 0x007C 0x02AC 0x0618 0x01 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x007C 0x02AC 0x04A4 0x02 0x02
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TPM6_CH3 0x007C 0x02AC 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TMS 0x007C 0x02AC 0x0600 0x05 0x01
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_LPSPI5_PCS1 0x007C 0x02AC 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x007C 0x02AC 0x04B0 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_GPIO2_IO_28 0x0080 0x02B0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_LPI2C3_SDA 0x0080 0x02B0 0x0530 0x01 0x01
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_CAN3_TX 0x0080 0x02B0 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_28 0x0080 0x02B0 0x0000 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_GPIO2_IO_29 0x0084 0x02B4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_LPI2C3_SCL 0x0084 0x02B4 0x052C 0x01 0x01
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_CAN3_RX 0x0084 0x02B4 0x04A8 0x02 0x01
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_29 0x0084 0x02B4 0x0000 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_GPIO2_IO_30 0x0088 0x02B8 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x0088 0x02B8 0x0538 0x01 0x01
+#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0088 0x02B8 0x04B4 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_GPIO2_IO_31 0x008C 0x02BC 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x008C 0x02BC 0x0534 0x01 0x01
+#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x008C 0x02BC 0x04B8 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_GPIO5_IO_12 0x0090 0x02C0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x02C0 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPUART6_TX 0x0090 0x02C0 0x05AC 0x02 0x01
+#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0090 0x02C0 0x0564 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_GPIO5_IO_13 0x0094 0x02C4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPUART6_RX 0x0094 0x02C4 0x05A8 0x02 0x01
+#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0094 0x02C4 0x0560 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x0098 0x02C8 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0098 0x02C8 0x05A4 0x02 0x01
+#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0098 0x02C8 0x055C 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_GPIO5_IO_15 0x009C 0x02CC 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPUART6_RTS_B 0x009C 0x02CC 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPSPI4_SIN 0x009C 0x02CC 0x056C 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPSPI4_SOUT 0x00A0 0x02D0 0x0570 0x04 0x01
+#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x00A0 0x02D0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPUART7_TX 0x00A0 0x02D0 0x05B4 0x02 0x01
+
+#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_GPIO5_IO_17 0x00A4 0x02D4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPUART7_RX 0x00A4 0x02D4 0x05B0 0x02 0x01
+#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPSPI4_SCK 0x00A4 0x02D4 0x0568 0x04 0x01
+
+#define IMX952_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00D4 0x0304 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00D4 0x0304 0x0494 0x01 0x00
+#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x00D4 0x0304 0x04AC 0x04 0x00
+#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x00D4 0x0304 0x0000 0x05 0x00
+
+#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x00D8 0x0308 0x0000 0x05 0x00
+#define IMX952_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00D8 0x0308 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00D8 0x0308 0x0000 0x01 0x00
+#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x00D8 0x0308 0x04B0 0x04 0x00
+
+#define IMX952_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00DC 0x030C 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00DC 0x030C 0x0498 0x01 0x00
+#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x00DC 0x030C 0x0000 0x02 0x00
+#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_28 0x00DC 0x030C 0x0000 0x04 0x00
+#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_GPIO4_IO_28 0x00DC 0x030C 0x0000 0x05 0x00
+
+#define IMX952_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00E0 0x0310 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00E0 0x0310 0x0000 0x01 0x00
+#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x00E0 0x0310 0x04A8 0x02 0x00
+#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_29 0x00E0 0x0310 0x0000 0x04 0x00
+#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_GPIO4_IO_29 0x00E0 0x0310 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00E4 0x0314 0x0484 0x00 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_LPUART3_DCD_B 0x00E4 0x0314 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_I3C2_SCL 0x00E4 0x0314 0x0524 0x02 0x00
+#define IMX952_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00E4 0x0314 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_0 0x00E4 0x0314 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_GPIO4_IO_0 0x00E4 0x0314 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00E8 0x0318 0x0488 0x00 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_LPUART3_RIN_B 0x00E8 0x0318 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_I3C2_SDA 0x00E8 0x0318 0x0528 0x02 0x00
+#define IMX952_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00E8 0x0318 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_1 0x00E8 0x0318 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_GPIO4_IO_1 0x00E8 0x0318 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00EC 0x031C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_CAN2_TX 0x00EC 0x031C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00EC 0x031C 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_2 0x00EC 0x031C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_GPIO4_IO_2 0x00EC 0x031C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00F0 0x0320 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00F0 0x0320 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_CAN2_RX 0x00F0 0x0320 0x04A4 0x02 0x01
+#define IMX952_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00F0 0x0320 0x0480 0x03 0x00
+#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_3 0x00F0 0x0320 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_GPIO4_IO_3 0x00F0 0x0320 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00F4 0x0324 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_LPUART3_RTS_B 0x00F4 0x0324 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR 0x00F4 0x0324 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00F4 0x0324 0x047C 0x03 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_4 0x00F4 0x0324 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_GPIO4_IO_4 0x00F4 0x0324 0x0000 0x05 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR_B 0x00F4 0x0324 0x0000 0x06 0x00
+#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00F4 0x0324 0x0000 0x07 0x00
+
+#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00F8 0x0328 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_LPUART3_TX 0x00F8 0x0328 0x0588 0x01 0x00
+#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00F8 0x0328 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_5 0x00F8 0x0328 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_GPIO4_IO_5 0x00F8 0x0328 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00FC 0x032C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_LPUART3_DTR_B 0x00FC 0x032C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00FC 0x032C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_6 0x00FC 0x032C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_6 0x00FC 0x032C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x0100 0x0330 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RMII_REF50_CLK_OUT 0x0100 0x0330 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_7 0x0100 0x0330 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_GPIO4_IO_7 0x0100 0x0330 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x0104 0x0334 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_LPUART3_DSR_B 0x0104 0x0334 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x0104 0x0334 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x0104 0x0334 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_8 0x0104 0x0334 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_8 0x0104 0x0334 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x0108 0x0338 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0108 0x0338 0x048C 0x01 0x00
+#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_9 0x0108 0x0338 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_GPIO4_IO_9 0x0108 0x0338 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x010C 0x033C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_LPUART3_RX 0x010C 0x033C 0x0584 0x01 0x00
+#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x010C 0x033C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_10 0x010C 0x033C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_GPIO4_IO_10 0x010C 0x033C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x0110 0x0340 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0110 0x0340 0x0580 0x01 0x00
+#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x0110 0x0340 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPTMR2_ALT0 0x0110 0x0340 0x0574 0x03 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_11 0x0110 0x0340 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_GPIO4_IO_11 0x0110 0x0340 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x0114 0x0344 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0114 0x0344 0x048C 0x02 0x01
+#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_LPTMR2_ALT1 0x0114 0x0344 0x0578 0x03 0x00
+#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_12 0x0114 0x0344 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_GPIO4_IO_12 0x0114 0x0344 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x0118 0x0348 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0118 0x0348 0x057C 0x03 0x00
+#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_13 0x0118 0x0348 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_GPIO4_IO_13 0x0118 0x0348 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x011C 0x034C 0x0484 0x00 0x01
+#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_LPUART4_DCD_B 0x011C 0x034C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x011C 0x034C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_14 0x011C 0x034C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_GPIO4_IO_14 0x011C 0x034C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x0120 0x0350 0x0488 0x00 0x01
+#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_LPUART4_RIN_B 0x0120 0x0350 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x0120 0x0350 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_15 0x0120 0x0350 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_GPIO4_IO_15 0x0120 0x0350 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_0 0x0124 0x0354 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_16 0x0124 0x0354 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_GPIO4_IO_16 0x0124 0x0354 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x0124 0x0354 0x0000 0x00 0x00
+
+#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x0128 0x0358 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x0128 0x0358 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_1 0x0128 0x0358 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x0128 0x0358 0x05D0 0x03 0x00
+#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_17 0x0128 0x0358 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_GPIO4_IO_17 0x0128 0x0358 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x012C 0x035C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_LPUART4_RTS_B 0x012C 0x035C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_2 0x012C 0x035C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x012C 0x035C 0x05CC 0x03 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_18 0x012C 0x035C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_GPIO4_IO_18 0x012C 0x035C 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x012C 0x035C 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0130 0x0360 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_LPUART4_TX 0x0130 0x0360 0x0594 0x01 0x00
+#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_3 0x0130 0x0360 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x0130 0x0360 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_19 0x0130 0x0360 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_GPIO4_IO_19 0x0130 0x0360 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0130 0x0360 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0134 0x0364 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_LPUART4_DTR_B 0x0134 0x0364 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0134 0x0364 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0134 0x0364 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_20 0x0134 0x0364 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_20 0x0134 0x0364 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x0138 0x0368 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RMII_REF50_CLK_OUT 0x0138 0x0368 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x0138 0x0368 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_21 0x0138 0x0368 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_GPIO4_IO_21 0x0138 0x0368 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x013C 0x036C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_LPUART4_DSR_B 0x013C 0x036C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_0 0x013C 0x036C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_22 0x013C 0x036C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_22 0x013C 0x036C 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x013C 0x036C 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0140 0x0370 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0140 0x0370 0x0490 0x01 0x00
+#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_1 0x0140 0x0370 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x0140 0x0370 0x05C8 0x03 0x00
+#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_23 0x0140 0x0370 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_GPIO4_IO_23 0x0140 0x0370 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0144 0x0374 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_LPUART4_RX 0x0144 0x0374 0x0590 0x01 0x00
+#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_2 0x0144 0x0374 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x0144 0x0374 0x05C0 0x03 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_24 0x0144 0x0374 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_GPIO4_IO_24 0x0144 0x0374 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0144 0x0374 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x0148 0x0378 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_3 0x0148 0x0378 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x0148 0x0378 0x05C4 0x03 0x00
+#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_25 0x0148 0x0378 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_GPIO4_IO_25 0x0148 0x0378 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x0148 0x0378 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x014C 0x037C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_LPUART4_CTS_B 0x014C 0x037C 0x058C 0x01 0x00
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x014C 0x037C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x014C 0x037C 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_26 0x014C 0x037C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_GPIO4_IO_26 0x014C 0x037C 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x014C 0x037C 0x0490 0x06 0x01
+
+#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0150 0x0380 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0150 0x0380 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_27 0x0150 0x0380 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_GPIO4_IO_27 0x0150 0x0380 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0154 0x0384 0x04DC 0x04 0x01
+#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_GPIO3_IO_8 0x0154 0x0384 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x0154 0x0384 0x0000 0x00 0x00
+
+#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x0158 0x0388 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0158 0x0388 0x04E0 0x04 0x01
+#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_GPIO3_IO_9 0x0158 0x0388 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x015C 0x038C 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x015C 0x038C 0x04E4 0x04 0x01
+#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_GPIO3_IO_10 0x015C 0x038C 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x0160 0x0390 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x0160 0x0390 0x04E8 0x04 0x01
+#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_GPIO3_IO_11 0x0160 0x0390 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x0164 0x0394 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x0164 0x0394 0x0624 0x01 0x01
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0164 0x0394 0x04EC 0x04 0x01
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_GPIO3_IO_12 0x0164 0x0394 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0164 0x0394 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x0168 0x0398 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x0168 0x0398 0x064C 0x01 0x00
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0168 0x0398 0x04F0 0x04 0x01
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_GPIO3_IO_13 0x0168 0x0398 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x016C 0x039C 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x016C 0x039C 0x0638 0x01 0x00
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x016C 0x039C 0x04F4 0x04 0x01
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_GPIO3_IO_14 0x016C 0x039C 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x016C 0x039C 0x066C 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x0170 0x03A0 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x0170 0x03A0 0x063C 0x01 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_RESET_B 0x0170 0x03A0 0x0000 0x02 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x0170 0x03A0 0x04F8 0x04 0x01
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_GPIO3_IO_15 0x0170 0x03A0 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x0170 0x03A0 0x0670 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x0174 0x03A4 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x0174 0x03A4 0x0640 0x01 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_CD_B 0x0174 0x03A4 0x0000 0x02 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0174 0x03A4 0x04FC 0x04 0x01
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_GPIO3_IO_16 0x0174 0x03A4 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x0174 0x03A4 0x0674 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x0178 0x03A8 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x0178 0x03A8 0x0644 0x01 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_WP 0x0178 0x03A8 0x0000 0x02 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0178 0x03A8 0x0500 0x04 0x01
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_GPIO3_IO_17 0x0178 0x03A8 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x0178 0x03A8 0x0678 0x06 0x00
+
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x017C 0x03AC 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI1_A_DQS 0x017C 0x03AC 0x0620 0x01 0x00
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x017C 0x03AC 0x0504 0x04 0x01
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_GPIO3_IO_18 0x017C 0x03AC 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x017C 0x03AC 0x0654 0x06 0x00
+
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x0180 0x03B0 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_WP 0x0180 0x03B0 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0180 0x03B0 0x057C 0x02 0x01
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x0180 0x03B0 0x0508 0x04 0x01
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_GPIO3_IO_19 0x0180 0x03B0 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0180 0x03B0 0x0478 0x06 0x01
+
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x0184 0x03B4 0x0604 0x00 0x01
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x0184 0x03B4 0x061C 0x01 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x0184 0x03B4 0x0000 0x02 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x0184 0x03B4 0x05D8 0x03 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0184 0x03B4 0x050C 0x04 0x01
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_GPIO3_IO_20 0x0184 0x03B4 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x0184 0x03B4 0x0658 0x06 0x00
+
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x0188 0x03B8 0x0608 0x00 0x01
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x0188 0x03B8 0x0648 0x01 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x0188 0x03B8 0x0000 0x02 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x0188 0x03B8 0x05E8 0x03 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0188 0x03B8 0x0510 0x04 0x01
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_GPIO3_IO_21 0x0188 0x03B8 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI_SLV_CS 0x0188 0x03B8 0x0650 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x018C 0x03BC 0x060C 0x00 0x01
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x018C 0x03BC 0x0628 0x01 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x018C 0x03BC 0x0000 0x02 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x018C 0x03BC 0x05D4 0x03 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x018C 0x03BC 0x0514 0x04 0x01
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_GPIO3_IO_22 0x018C 0x03BC 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x018C 0x03BC 0x065C 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x0190 0x03C0 0x0610 0x00 0x01
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x0190 0x03C0 0x062C 0x01 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x0190 0x03C0 0x05DC 0x02 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x0190 0x03C0 0x0000 0x03 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x0190 0x03C0 0x0518 0x04 0x01
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_GPIO3_IO_23 0x0190 0x03C0 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x0190 0x03C0 0x0660 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x0194 0x03C4 0x0614 0x00 0x01
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x0194 0x03C4 0x0630 0x01 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x0194 0x03C4 0x05E0 0x02 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x0194 0x03C4 0x05F0 0x03 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0194 0x03C4 0x051C 0x04 0x01
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_GPIO3_IO_24 0x0194 0x03C4 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x0194 0x03C4 0x0664 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x0198 0x03C8 0x0618 0x00 0x01
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x0198 0x03C8 0x0634 0x01 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x0198 0x03C8 0x05E4 0x02 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x0198 0x03C8 0x05EC 0x03 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0198 0x03C8 0x0520 0x04 0x01
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_GPIO3_IO_25 0x0198 0x03C8 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x0198 0x03C8 0x0668 0x06 0x00
+
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x019C 0x03CC 0x0628 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_4 0x019C 0x03CC 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x019C 0x03CC 0x05CC 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_RX_DATA_1 0x019C 0x03CC 0x0000 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x019C 0x03CC 0x065C 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_GPIO5_IO_0 0x019C 0x03CC 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x01A0 0x03D0 0x062C 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_5 0x01A0 0x03D0 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x01A0 0x03D0 0x05D0 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_DATA_1 0x01A0 0x03D0 0x0000 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x01A0 0x03D0 0x0660 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_GPIO5_IO_1 0x01A0 0x03D0 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x01A4 0x03D4 0x0630 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_6 0x01A4 0x03D4 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x01A4 0x03D4 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x01A4 0x03D4 0x0664 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x01A4 0x03D4 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x01A8 0x03D8 0x0634 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_7 0x01A8 0x03D8 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x01A8 0x03D8 0x05C4 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x01A8 0x03D8 0x0668 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_GPIO5_IO_3 0x01A8 0x03D8 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x01AC 0x03DC 0x0638 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x01AC 0x03DC 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x01AC 0x03DC 0x05DC 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x01AC 0x03DC 0x066C 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_GPIO5_IO_4 0x01AC 0x03DC 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x01B0 0x03E0 0x063C 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x01B0 0x03E0 0x05F0 0x01 0x01
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x01B0 0x03E0 0x05E0 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_6 0x01B0 0x03E0 0x049C 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x01B0 0x03E0 0x0670 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_GPIO5_IO_5 0x01B0 0x03E0 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x01B4 0x03E4 0x0640 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x01B4 0x03E4 0x05EC 0x01 0x01
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x01B4 0x03E4 0x05E4 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_7 0x01B4 0x03E4 0x04A0 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x01B4 0x03E4 0x0674 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_GPIO5_IO_6 0x01B4 0x03E4 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x01B8 0x03E8 0x0644 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x01B8 0x03E8 0x05D8 0x01 0x01
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x01B8 0x03E8 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x01B8 0x03E8 0x0678 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_GPIO5_IO_7 0x01B8 0x03E8 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x01BC 0x03EC 0x0620 0x00 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x01BC 0x03EC 0x05E8 0x01 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x01BC 0x03EC 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_6 0x01BC 0x03EC 0x049C 0x03 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x01BC 0x03EC 0x0654 0x04 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_GPIO5_IO_8 0x01BC 0x03EC 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x01C0 0x03F0 0x061C 0x00 0x01
+#define IMX952_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_4 0x01C0 0x03F0 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x01C0 0x03F0 0x05C8 0x02 0x01
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x01C0 0x03F0 0x0658 0x04 0x01
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_GPIO5_IO_9 0x01C0 0x03F0 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x01C4 0x03F4 0x0648 0x00 0x01
+#define IMX952_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_5 0x01C4 0x03F4 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x01C4 0x03F4 0x05C0 0x02 0x01
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI_SLV_CS 0x01C4 0x03F4 0x0650 0x04 0x01
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_GPIO5_IO_10 0x01C4 0x03F4 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x01C8 0x03F8 0x064C 0x00 0x01
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x01C8 0x03F8 0x05D4 0x01 0x01
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x01C8 0x03F8 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_7 0x01C8 0x03F8 0x04A0 0x03 0x01
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x01C8 0x03F8 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_USDHC2_CD_B 0x01CC 0x03FC 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01CC 0x03FC 0x0494 0x01 0x01
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_I3C2_SCL 0x01CC 0x03FC 0x0524 0x02 0x01
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x01CC 0x03FC 0x04BC 0x04 0x01
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x01CC 0x03FC 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x01D0 0x0400 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01D0 0x0400 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_I3C2_SDA 0x01D0 0x0400 0x0528 0x02 0x01
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x01D0 0x0400 0x04C0 0x04 0x01
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_GPIO3_IO_1 0x01D0 0x0400 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01D0 0x0400 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x01D4 0x0404 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01D4 0x0404 0x0498 0x01 0x01
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR 0x01D4 0x0404 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR_B 0x01D4 0x0404 0x0000 0x03 0x00
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x01D4 0x0404 0x04C4 0x04 0x01
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_GPIO3_IO_2 0x01D4 0x0404 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01D4 0x0404 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x01D8 0x0408 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01D8 0x0408 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_CAN2_TX 0x01D8 0x0408 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x01D8 0x0408 0x04C8 0x04 0x01
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_GPIO3_IO_3 0x01D8 0x0408 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01D8 0x0408 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x01DC 0x040C 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01DC 0x040C 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_CAN2_RX 0x01DC 0x040C 0x04A4 0x02 0x03
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x01DC 0x040C 0x04CC 0x04 0x01
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_GPIO3_IO_4 0x01DC 0x040C 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x01E0 0x0410 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01E0 0x0410 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01E0 0x0410 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x01E0 0x0410 0x04D0 0x04 0x01
+#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_GPIO3_IO_5 0x01E0 0x0410 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x01E4 0x0414 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_LPTMR2_ALT0 0x01E4 0x0414 0x0574 0x01 0x01
+#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01E4 0x0414 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01E4 0x0414 0x0000 0x03 0x00
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x01E4 0x0414 0x04D4 0x04 0x01
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_GPIO3_IO_6 0x01E4 0x0414 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_USDHC2_RESET_B 0x01E8 0x0418 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_LPTMR2_ALT1 0x01E8 0x0418 0x0578 0x01 0x01
+#define IMX952_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01E8 0x0418 0x0000 0x03 0x00
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x01E8 0x0418 0x04D8 0x04 0x01
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x01E8 0x0418 0x0000 0x05 0x00
+
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01EC 0x041C 0x0000 0x00 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01EC 0x041C 0x0000 0x01 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01EC 0x041C 0x0000 0x02 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01EC 0x041C 0x0000 0x03 0x00
+#define IMX952_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01EC 0x041C 0x0000 0x04 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_0 0x01EC 0x041C 0x0000 0x05 0x00
+
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01F0 0x0420 0x0000 0x00 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01F0 0x0420 0x0000 0x01 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01F0 0x0420 0x0000 0x02 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01F0 0x0420 0x0000 0x03 0x00
+#define IMX952_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01F0 0x0420 0x0000 0x04 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_1 0x01F0 0x0420 0x0000 0x05 0x00
+
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01F4 0x0424 0x0000 0x00 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01F4 0x0424 0x0000 0x01 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01F4 0x0424 0x0000 0x02 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01F4 0x0424 0x0000 0x03 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01F4 0x0424 0x0000 0x04 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_2 0x01F4 0x0424 0x0000 0x05 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01F4 0x0424 0x0000 0x06 0x00
+
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01F8 0x0428 0x0000 0x00 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01F8 0x0428 0x0000 0x02 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01F8 0x0428 0x0000 0x03 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01F8 0x0428 0x0000 0x04 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_3 0x01F8 0x0428 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01FC 0x042C 0x0000 0x00 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_UART_CSSI_RX 0x01FC 0x042C 0x0000 0x01 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01FC 0x042C 0x0000 0x02 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01FC 0x042C 0x0000 0x03 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_4 0x01FC 0x042C 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x0200 0x0430 0x0000 0x00 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_UART_CSSI_TX 0x0200 0x0430 0x0000 0x01 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x0200 0x0430 0x0000 0x02 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x0200 0x0430 0x0000 0x03 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_5 0x0200 0x0430 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x0204 0x0434 0x0000 0x00 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x0204 0x0434 0x0000 0x01 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x0204 0x0434 0x0000 0x02 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x0204 0x0434 0x0000 0x03 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x0204 0x0434 0x0474 0x04 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_6 0x0204 0x0434 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x0208 0x0438 0x0000 0x00 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x0208 0x0438 0x0000 0x01 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x0208 0x0438 0x0000 0x02 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x0208 0x0438 0x0000 0x03 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_7 0x0208 0x0438 0x0000 0x05 0x00
+
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x020C 0x043C 0x0000 0x00 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x020C 0x043C 0x0000 0x01 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT0 0x020C 0x043C 0x0000 0x04 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x020C 0x043C 0x0000 0x05 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x020C 0x043C 0x0000 0x06 0x00
+
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x0210 0x0440 0x0464 0x00 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x0210 0x0440 0x0000 0x01 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x0210 0x0440 0x0000 0x02 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x0210 0x0440 0x0000 0x03 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT1 0x0210 0x0440 0x0000 0x04 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x0210 0x0440 0x0000 0x05 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x0210 0x0440 0x0460 0x06 0x00
+
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_1 0x0214 0x0444 0x0468 0x00 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_NMI 0x0214 0x0444 0x0000 0x01 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x0214 0x0444 0x0000 0x02 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x0214 0x0444 0x0000 0x03 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT2 0x0214 0x0444 0x0000 0x04 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_10 0x0214 0x0444 0x0000 0x05 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0214 0x0444 0x0478 0x06 0x00
+
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x0218 0x0448 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_1 0x0218 0x0448 0x0000 0x01 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x0218 0x0448 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x0218 0x0448 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x0218 0x0448 0x0000 0x04 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x0218 0x0448 0x0000 0x05 0x00
+
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x021C 0x044C 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x021C 0x044C 0x0000 0x01 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x021C 0x044C 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x021C 0x044C 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x021C 0x044C 0x0460 0x04 0x01
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x021C 0x044C 0x0000 0x05 0x00
+
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x0220 0x0450 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x0220 0x0450 0x0000 0x01 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x0220 0x0450 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x0220 0x0450 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x0220 0x0450 0x0000 0x04 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x0220 0x0450 0x0000 0x05 0x00
+
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x0224 0x0454 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x0224 0x0454 0x0474 0x01 0x01
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x0224 0x0454 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x0224 0x0454 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x0224 0x0454 0x0000 0x04 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x0224 0x0454 0x0000 0x05 0x00
+
+#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x0228 0x0458 0x0000 0x00 0x00
+#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x0228 0x0458 0x0000 0x01 0x00
+#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_15 0x0228 0x0458 0x0000 0x05 0x00
+#endif /* __DTS_IMX952_PINFUNC_H__ */
diff --git a/dts/upstream/src/arm64/freescale/imx952-power.h b/dts/upstream/src/arm64/freescale/imx952-power.h
new file mode 100644
index 00000000000..1d0fb8c93e2
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx952-power.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX952_POWER_H__
+#define __IMX952_POWER_H__
+
+#define IMX952_PD_ANA 0
+#define IMX952_PD_AON 1
+#define IMX952_PD_BBSM 2
+#define IMX952_PD_CAMERA 3
+#define IMX952_PD_CCMSRCGPC 4
+#define IMX952_PD_A55C0 5
+#define IMX952_PD_A55C1 6
+#define IMX952_PD_A55C2 7
+#define IMX952_PD_A55C3 8
+#define IMX952_PD_A55P 9
+#define IMX952_PD_DDR 10
+#define IMX952_PD_DISPLAY 11
+#define IMX952_PD_GPU 12
+#define IMX952_PD_HSIO_TOP 13
+#define IMX952_PD_HSIO_WAON 14
+#define IMX952_PD_M7 15
+#define IMX952_PD_NETC 16
+#define IMX952_PD_NOC 17
+#define IMX952_PD_NPU 18
+#define IMX952_PD_VPU 19
+#define IMX952_PD_WAKEUP 20
+
+#define IMX952_PERF_M33 0
+#define IMX952_PERF_WAKEUP 1
+#define IMX952_PERF_M7 2
+#define IMX952_PERF_DRAM 3
+#define IMX952_PERF_HSIO 4
+#define IMX952_PERF_NPU 5
+#define IMX952_PERF_NOC 6
+#define IMX952_PERF_A55 7
+#define IMX952_PERF_GPU 8
+#define IMX952_PERF_VPU 9
+#define IMX952_PERF_CAM 10
+#define IMX952_PERF_DISP 11
+
+#endif
diff --git a/dts/upstream/src/arm64/freescale/imx952.dtsi b/dts/upstream/src/arm64/freescale/imx952.dtsi
new file mode 100644
index 00000000000..91fe4916ac0
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx952.dtsi
@@ -0,0 +1,1266 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx952-clock.h"
+#include "imx952-pinfunc.h"
+#include "imx952-power.h"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "dummy";
+ };
+
+ clk_ldb_pll_pixel: clock-ldb-pll-div7 {
+ compatible = "fixed-factor-clock";
+ clocks = <&scmi_clk IMX952_CLK_LDBPLL>;
+ #clock-cells = <0>;
+ clock-div = <7>;
+ clock-mult = <1>;
+ clock-output-names = "ldb_pll_div7";
+ };
+
+ clk_osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_pd_wait: cpu-pd-wait {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ A55_2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l2>;
+ };
+
+ A55_3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l3>;
+ };
+
+ l2_cache_l0: l2-cache-l0 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l1: l2-cache-l1 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l2: l2-cache-l2 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l3: l2-cache-l3 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <3>;
+ cache-unified;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A55_0>;
+ };
+
+ core1 {
+ cpu = <&A55_1>;
+ };
+
+ core2 {
+ cpu = <&A55_2>;
+ };
+
+ core3 {
+ cpu = <&A55_3>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>;
+ shmem = <&scmi_buf0>, <&scmi_buf1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ arm,max-rx-timeout-ms = <5000>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_sys_power: protocol@12 {
+ reg = <0x12>;
+ };
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ scmi_iomuxc: protocol@19 {
+ reg = <0x19>;
+ };
+
+ scmi_lmm: protocol@80 {
+ reg = <0x80>;
+ };
+
+ scmi_bbm: protocol@81 {
+ reg = <0x81>;
+ };
+
+ scmi_cpu: protocol@82 {
+ reg = <0x82>;
+ };
+
+ scmi_misc: protocol@84 {
+ reg = <0x84>;
+ };
+ };
+ };
+
+ gic: interrupt-controller@48000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x48000000 0 0x10000>,
+ <0 0x48060000 0 0xc0000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ dma-noncoherent;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ its: msi-controller@48040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0 0x48040000 0 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ dma-noncoherent;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ clocks = <&clk_dummy>;
+ clock-names = "main_clk";
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ clocks = <&clk_dummy>;
+ clock-names = "main_clk";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>,
+ <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>;
+
+ aips2: bus@42000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x42000000 0x0 0x800000>;
+ ranges = <0x42000000 0x0 0x42000000 0x8000000>,
+ <0x28000000 0x0 0x28000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mu7: mailbox@42050000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x42050000 0x10000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ wdog3: watchdog@420b0000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x420b0000 0x10000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ };
+
+ tpm3: pwm@42100000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42100000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm4: pwm@42110000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42110000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_TPM4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm5: pwm@42120000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42120000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_TPM5>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm6: pwm@42130000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42130000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_TPM6>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i3c2: i3c@42140000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x42140000 0x10000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_I3C2SLOW>,
+ <&clk_dummy>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c3: i2c@42150000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42150000 0x10000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C3>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@42160000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42160000 0x10000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C4>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi3: spi@42170000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42170000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI3>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi4: spi@42180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42180000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI4>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpuart3: serial@42190000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42190000 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART3>;
+ clock-names = "ipg";
+ dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart4: serial@421a0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x421a0000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART4>;
+ clock-names = "ipg";
+ dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart5: serial@421b0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x421b0000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART5>;
+ clock-names = "ipg";
+ dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart6: serial@421c0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x421c0000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART6>;
+ clock-names = "ipg";
+ dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ flexcan2: can@421d0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x421d0000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_CAN2>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ flexcan3: can@42220000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x42220000 0x10000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_CAN3>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ lpuart7: serial@422b0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x422b0000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART7>;
+ clock-names = "ipg";
+ dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart8: serial@422c0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x422c0000 0x1000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART8>;
+ clock-names = "ipg";
+ dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@422d0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x422d0000 0x10000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C5>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c6: i2c@422e0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x422e0000 0x10000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C6>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c7: i2c@422f0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x422f0000 0x10000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C7>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c8: i2c@42300000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42300000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C8>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi5: spi@42310000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42310000 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI5>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi6: spi@42320000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42320000 0x10000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI6>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi7: spi@42330000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42330000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI7>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi8: spi@42340000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42340000 0x10000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI8>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mu8: mailbox@42350000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x42350000 0x10000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips3: bus@42800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0 0x42800000 0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x42800000 0x0 0x42800000 0x800000>;
+
+ edma2: dma-controller@42800000 {
+ compatible = "fsl,imx95-edma5";
+ reg = <0x42800000 0x210000>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "dma";
+ #dma-cells = <3>;
+ dma-channels = <64>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; //error irq
+ };
+
+ usdhc1: mmc@42c20000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42c20000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX952_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@42c30000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42c30000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX952_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <200000000>;
+ bus-width = <4>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@42c40000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42c40000 0x10000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX952_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step = <2>;
+ status = "disabled";
+ };
+ };
+
+ gpio2: gpio@43810000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43810000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 4 32>;
+ ngpios = <32>;
+ };
+
+ gpio3: gpio@43820000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43820000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>,
+ <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>;
+ ngpios = <32>;
+ };
+
+ gpio4: gpio@43840000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43840000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>;
+ ngpios = <30>;
+ };
+
+ gpio5: gpio@43850000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43850000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>;
+ ngpios = <18>;
+ };
+
+ aips1: bus@44000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x44000000 0x0 0x800000>;
+ ranges = <0x44000000 0x0 0x44000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ edma1: dma-controller@44000000 {
+ compatible = "fsl,imx93-edma3";
+ reg = <0x44000000 0x210000>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "dma";
+ #dma-cells = <3>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; //error irq
+ };
+
+ mu1: mailbox@44220000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44220000 0x10000>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ system_counter: timer@44290000 {
+ compatible = "nxp,imx95-sysctr-timer";
+ reg = <0x44290000 0x30000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_osc_24m>;
+ clock-names = "per";
+ nxp,no-divider;
+ };
+
+ i3c1: i3c@44330000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x44330000 0x10000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>,
+ <&scmi_clk IMX952_CLK_I3C1SLOW>,
+ <&clk_dummy>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c1: i2c@44340000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44340000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C1>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c2: i2c@44350000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44350000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C2>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi1: spi@44360000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x44360000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI1>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi2: spi@44370000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x44370000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI2>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpuart1: serial@44380000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44380000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART1>;
+ clock-names = "ipg";
+ dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart2: serial@44390000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44390000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART2>;
+ clock-names = "ipg";
+ dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ flexcan1: can@443a0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x443a0000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>,
+ <&scmi_clk IMX952_CLK_CAN1>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ adc1: adc@44530000 {
+ compatible = "nxp,imx93-adc";
+ reg = <0x44530000 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_ADC>;
+ clock-names = "ipg";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ mu2: mailbox@445b0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445b0000 0x1000>;
+ ranges;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #mbox-cells = <2>;
+
+ sram0: sram@445b1000 {
+ compatible = "mmio-sram";
+ reg = <0x445b1000 0x400>;
+ ranges = <0x0 0x445b1000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_buf0: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ scmi_buf1: scmi-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+
+ };
+
+ mu3: mailbox@445d0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445d0000 0x10000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu4: mailbox@445f0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445f0000 0x10000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu5: mailbox@44610000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44610000 0x10000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu6: mailbox@44630000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44630000 0x10000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ v2x_mu0: mailbox@47300000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu2: mailbox@47320000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu3: mailbox@47330000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu4: mailbox@47340000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47340000 0x0 0x10000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu: mailbox@47350000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47350000 0x0 0x10000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ /* GPIO1 is under exclusive control of System Manager */
+ gpio1: gpio@47400000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x47400000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_M33>,
+ <&scmi_clk IMX952_CLK_M33>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 123 16>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ elemu0: mailbox@47520000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47520000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu1: mailbox@47530000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu2: mailbox@47540000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47540000 0x0 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu3: mailbox@47550000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47550000 0x0 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ elemu4: mailbox@47560000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu5: mailbox@47570000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47570000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ usb1: usb@4c100000 {
+ compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x0 0x4c100000 0x0 0x200>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>,
+ <&scmi_clk IMX952_CLK_OSC32K>;
+ clock-names = "usb_ctrl_root", "usb_wakeup";
+ power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>;
+ phys = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@4c100200 {
+ compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ #index-cells = <1>;
+ reg = <0x0 0x4c100200 0x0 0x200>,
+ <0x0 0x4c010010 0x0 0x4>;
+ };
+
+ usb2: usb@4c200000 {
+ compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x0 0x4c200000 0x0 0x200>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>,
+ <&scmi_clk IMX952_CLK_OSC32K>;
+ clock-names = "usb_ctrl_root", "usb_wakeup";
+ power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>;
+ phys = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@4c200200 {
+ compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ #index-cells = <1>;
+ reg = <0x0 0x4c200200 0x0 0x200>,
+ <0x0 0x4c010014 0x0 0x4>;
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (9 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-06 0:51 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support alice.guo
11 siblings, 1 reply; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Add U-Boot specific device tree configuration for i.MX952 EVK board.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/imx952-evk-u-boot.dtsi | 58 +++++++
arch/arm/dts/imx952-u-boot.dtsi | 327 ++++++++++++++++++++++++++++++++++++
2 files changed, 385 insertions(+)
diff --git a/arch/arm/dts/imx952-evk-u-boot.dtsi b/arch/arm/dts/imx952-evk-u-boot.dtsi
new file mode 100644
index 00000000000..1b2c314a41b
--- /dev/null
+++ b/arch/arm/dts/imx952-evk-u-boot.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "imx952-u-boot.dtsi"
+
+&i2c3_pcal6408 {
+ compatible = "ti,tca6408";
+ label = "i2c3_io";
+};
+
+&i2c4_pcal6408 {
+ compatible = "ti,tca6408";
+ label = "i2c4_io";
+};
+
+&pcal6416 {
+ compatible = "ti,tca6416";
+ label = "i2c6_io";
+};
+
+&pcal6524 {
+ label = "i2c7_io";
+};
+
+&usb1 {
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ /delete-property/power-domains;
+ bootph-pre-ram;
+ extcon = <&ptn5110>;
+};
+
+&usb2 {
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ /delete-property/power-domains;
+ bootph-pre-ram;
+};
+
+&usbmisc1 {
+ bootph-pre-ram;
+};
+
+&usbmisc2 {
+ bootph-pre-ram;
+};
+
+&usbphynop1 {
+ bootph-pre-ram;
+};
+
+&usbphynop2 {
+ bootph-pre-ram;
+};
+
+&wdog3 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi
new file mode 100644
index 00000000000..208931ba884
--- /dev/null
+++ b/arch/arm/dts/imx952-u-boot.dtsi
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+/ {
+ binman {
+ multiple-images;
+
+ m33-oei-ddrfw {
+ pad-byte = <0x00>;
+ align-size = <0x8>;
+ filename = "m33-oei-ddrfw.bin";
+
+ oei-m33-ddr {
+ align-size = <0x4>;
+ filename = "oei-m33-ddr.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr {
+ type = "nxp-header-ddrfw";
+
+ imx-lpddr-imem {
+ filename = "lpddr4x_imem_v202409.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr-dmem {
+ filename = "lpddr4x_dmem_v202409.bin";
+ type = "blob-ext";
+ };
+ };
+
+ imx-lpddr-qb {
+ type = "nxp-header-ddrfw";
+
+ imx-lpddr-imem-qb {
+ filename = "lpddr4x_imem_qb_v202409.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr-dmem-qb {
+ filename = "lpddr4x_dmem_qb_v202409.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl {
+ type = "nxp-imx9image";
+ cfg-path = "spl/u-boot-spl.cfgout";
+ args;
+
+ cntr-version = <2>;
+ boot-from = "sd";
+ soc-type = "IMX9";
+ append = "mx952a0-ahab-container.img";
+ container;
+ dummy-ddr;
+ image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
+ hold = <0x10000>;
+ image1 = "m33", "m33_image.bin", "0x1ffc0000";
+ image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
+ dummy-v2x = <0x8b000000>;
+ };
+
+ u-boot {
+ type = "nxp-imx9image";
+ cfg-path = "u-boot-container.cfgout";
+ args;
+
+ cntr-version = <2>;
+ boot-from = "sd";
+ soc-type = "IMX9";
+ container;
+ image0 = "a55", "bl31.bin", "0x8a200000";
+ image1 = "a55", "u-boot.bin", "0x90200000";
+ };
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon";
+ };
+
+ aliases {
+ usb_gadget0 = &usbg1;
+ usb_gadget1 = &usbg2;
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usb1>;
+ bootph-pre-ram;
+ status = "okay";
+ };
+
+ usbg2: usbg2 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usb2>;
+ bootph-pre-ram;
+ status = "okay";
+ };
+
+ reg_m2_pwr: regulator-m2-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "M.2-power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * M.2 device only can be enabled(W_DISABLE1#) after all Power
+ * Rails reach their minimum operating voltage (PCI Express M.2
+ * Specification r5.1 3.1.4 Power-up Timing).
+ * Set a delay equal to the max value of Tsettle here.
+ */
+ startup-delay-us = <5000>;
+ };
+};
+
+&A55_0 {
+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_1 {
+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_2 {
+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_3 {
+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&aips1 {
+ bootph-all;
+};
+
+&aips2 {
+ bootph-all;
+};
+
+&aips3 {
+ bootph-all;
+};
+
+&clk_ext1 {
+ bootph-all;
+};
+
+&clk_dummy {
+ bootph-all;
+};
+
+&clk_osc_24m {
+ bootph-all;
+};
+
+&elemu1 {
+ status = "okay";
+ bootph-all;
+};
+
+&elemu3 {
+ status = "okay";
+ bootph-all;
+};
+
+&{/firmware} {
+ bootph-all;
+};
+
+&{/firmware/scmi} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@11} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@13} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@14} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@15} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@19} {
+ bootph-all;
+};
+
+&gpio1 {
+ reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
+};
+
+&gpio2 {
+ reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>;
+ bootph-pre-ram;
+ /*
+ * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2
+ * is assigned to M7, disable gpio2 here
+ */
+ status = "disabled";
+};
+
+&gpio3 {
+ reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>;
+ bootph-pre-ram;
+};
+
+&gpio4 {
+ reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>;
+ bootph-pre-ram;
+};
+
+&gpio5 {
+ reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>;
+ bootph-pre-ram;
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+};
+
+&mu2 {
+ bootph-all;
+};
+
+®_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&scmi_buf0 {
+ reg = <0x0 0x400>;
+ bootph-all;
+};
+
+&scmi_buf1 {
+ bootph-all;
+};
+
+&{/soc} {
+ bootph-all;
+};
+
+&sram0 {
+ bootph-all;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+};
+
+&scmi_iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ bootph-pre-ram;
+
+ fsl,pins = <
+ IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x3fe
+ IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e
+ IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x3fe
+ IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x3fe
+ >;
+ };
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
` (10 preceding siblings ...)
2026-02-05 13:55 ` [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK alice.guo
@ 2026-02-05 13:55 ` alice.guo
2026-02-05 15:45 ` Tom Rini
2026-02-06 1:24 ` Peng Fan
11 siblings, 2 replies; 33+ messages in thread
From: alice.guo @ 2026-02-05 13:55 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Ye Li,
Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
From: Peng Fan <peng.fan@nxp.com>
Add support for i.MX952 15x15 lpddr4x board support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/imx9/Kconfig | 14 ++
board/nxp/imx952_evk/Kconfig | 12 ++
board/nxp/imx952_evk/MAINTAINERS | 6 +
board/nxp/imx952_evk/Makefile | 14 ++
board/nxp/imx952_evk/imx952_evk.c | 297 ++++++++++++++++++++++++++++++++++++
board/nxp/imx952_evk/imx952_evk.env | 137 +++++++++++++++++
board/nxp/imx952_evk/spl.c | 115 ++++++++++++++
configs/imx952_evk_defconfig | 178 +++++++++++++++++++++
doc/board/nxp/imx952_evk.rst | 112 ++++++++++++++
doc/board/nxp/index.rst | 1 +
include/configs/imx952_evk.h | 31 ++++
12 files changed, 918 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0f6e737c0b9..bf6820de655 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -223,7 +223,7 @@ endif
ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
-ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),)
+ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94),$(CONFIG_IMX952))),)
SPL: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 716940930a6..2ba088c49c5 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -162,6 +162,19 @@ config TARGET_TORADEX_SMARC_IMX95
bool "Support Toradex SMARC iMX95"
select IMX95
+config TARGET_IMX952_EVK
+ bool "imx952_evk"
+ select CMD_REMOTEPROC
+ select IMX_SM_CPU
+ select IMX_SM_LMM
+ select IMX952
+ select REMOTEPROC_IMX
+ select REGMAP
+ select SYSCON
+ imply BOOTSTD_BOOTCOMMAND
+ imply BOOTSTD_FULL
+ imply OF_UPSTREAM
+
endchoice
source "board/nxp/imx91_evk/Kconfig"
@@ -175,5 +188,6 @@ source "board/variscite/imx93_var_som/Kconfig"
source "board/nxp/imx94_evk/Kconfig"
source "board/nxp/imx95_evk/Kconfig"
source "board/toradex/smarc-imx95/Kconfig"
+source "board/nxp/imx952_evk/Kconfig"
endif
diff --git a/board/nxp/imx952_evk/Kconfig b/board/nxp/imx952_evk/Kconfig
new file mode 100644
index 00000000000..96f01323aca
--- /dev/null
+++ b/board/nxp/imx952_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX952_EVK
+
+config SYS_BOARD
+ default "imx952_evk"
+
+config SYS_VENDOR
+ default "nxp"
+
+config SYS_CONFIG_NAME
+ default "imx952_evk"
+
+endif
diff --git a/board/nxp/imx952_evk/MAINTAINERS b/board/nxp/imx952_evk/MAINTAINERS
new file mode 100644
index 00000000000..cc004f9467e
--- /dev/null
+++ b/board/nxp/imx952_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX952 EVK BOARD
+M: Alice Guo <alice.guo@nxp.com>
+S: Maintained
+F: board/nxp/imx952_evk/
+F: include/configs/imx952_evk.h
+F: configs/imx952_evk_defconfig
diff --git a/board/nxp/imx952_evk/Makefile b/board/nxp/imx952_evk/Makefile
new file mode 100644
index 00000000000..1581721dc78
--- /dev/null
+++ b/board/nxp/imx952_evk/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright 2025-2026 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Add include path for NXP device tree header files from Linux.
+ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/
+
+obj-y += imx952_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c
new file mode 100644
index 00000000000..8b4b2083a20
--- /dev/null
+++ b/board/nxp/imx952_evk/imx952_evk.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <imx952-power.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <scmi_agent.h>
+#include <usb.h>
+
+#define PD_HSIO_TOP IMX952_PD_HSIO_TOP
+#define PD_NETC IMX952_PD_NETC
+#define PD_DISPLAY IMX952_PD_DISPLAY
+#define PD_CAMERA IMX952_PD_CAMERA
+
+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
+#define IMX_BOOT_IMAGE_GUID \
+ EFI_GUID(0x58a661f3, 0xe7c7, 0x4173, 0x80, 0x21, \
+ 0xa3, 0x1b, 0x95, 0xc8, 0x6e, 0x9b)
+
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = IMX_BOOT_IMAGE_GUID,
+ .fw_name = u"IMX952-EVK-RAW",
+ .image_index = 1,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
+int board_early_init_f(void)
+{
+ /* UART1: A55, UART2: M33, UART3: M7 */
+ init_uart_clk(0);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+ .i2c_bus = 6, /* i2c7 */
+ .addr = 0x50,
+ .port_type = TYPEC_PORT_DRP,
+ .disable_pd = true,
+};
+
+static int setup_typec(void)
+{
+ int ret;
+
+ debug("tcpc_init port 1\n");
+ ret = tcpc_init(&port, port_config, NULL);
+ if (ret) {
+ printf("%s: tcpc port init failed, err=%d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+#endif
+
+static int imx9_scmi_power_domain_enable(u32 domain, bool enable)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ return scmi_pwd_state_set(dev, 0, domain, enable ? 0 : BIT(30));
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ ret = imx9_scmi_power_domain_enable(PD_HSIO_TOP, true);
+ if (ret) {
+ printf("SCMI_POWWER_STATE_SET Failed for USB\n");
+ return ret;
+ }
+ } else if (index == 0 && init == USB_INIT_HOST) {
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ int ret = 0;
+
+ if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_disable_src_vbus(&port);
+#endif
+ }
+
+ return ret;
+}
+
+static void netc_phy_rst(const char *gpio_name, const char *label)
+{
+ int ret;
+ struct gpio_desc desc;
+
+ /* ENET_RST_B */
+ ret = dm_gpio_lookup_name(gpio_name, &desc);
+ if (ret) {
+ printf("%s lookup %s failed ret = %d\n", __func__, gpio_name, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&desc, label);
+ if (ret) {
+ printf("%s request %s failed ret = %d\n", __func__, label, ret);
+ return;
+ }
+
+ /* assert the ENET_RST_B */
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+ udelay(10000);
+ dm_gpio_set_value(&desc, 0); /* deassert the ENET_RST_B */
+ udelay(80000);
+}
+
+void netc_init(void)
+{
+ int ret;
+
+ ret = imx9_scmi_power_domain_enable(PD_NETC, false);
+ udelay(10000);
+
+ /* Power up the NETC MIX. */
+ ret = imx9_scmi_power_domain_enable(PD_NETC, true);
+ if (ret) {
+ printf("SCMI_POWWER_STATE_SET Failed for NETC MIX\n");
+ return;
+ }
+
+ netc_phy_rst("i2c6_io@21_13", "ENET1_RST_B");
+
+ pci_init();
+}
+
+static void pcie_setup(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = regulator_get_by_devname("regulator-m2-pwr", &dev);
+ if (ret) {
+ printf("Get regulator-m2-pwr regulator failed %d\n", ret);
+ return;
+ }
+
+ ret = regulator_set_enable_if_allowed(dev, true);
+ if (ret) {
+ printf("Enable regulator-m2-pwr regulator %d\n", ret);
+ return;
+ }
+}
+
+void lvds_backlight_on(void)
+{
+ /* None */
+}
+
+int board_init(void)
+{
+ int ret;
+
+ ret = imx9_scmi_power_domain_enable(PD_HSIO_TOP, true);
+ if (ret) {
+ printf("SCMI_POWWER_STATE_SET Failed for USB\n");
+ return ret;
+ }
+
+ imx9_scmi_power_domain_enable(PD_DISPLAY, false);
+ imx9_scmi_power_domain_enable(PD_CAMERA, false);
+
+#if defined(CONFIG_USB_TCPC)
+ setup_typec();
+#endif
+
+ pcie_setup();
+
+ netc_init();
+
+ lvds_backlight_on();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+ board_late_mmc_env_init();
+
+ env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+ env_set("sec_boot", "yes");
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ char *p, *b, *s;
+ char *token = NULL;
+ int i, ret = 0;
+ u64 base[CONFIG_NR_DRAM_BANKS] = {0};
+ u64 size[CONFIG_NR_DRAM_BANKS] = {0};
+
+ p = env_get("jh_root_mem");
+ if (!p)
+ return 0;
+
+ i = 0;
+ token = strtok(p, ",");
+ while (token) {
+ if (i >= CONFIG_NR_DRAM_BANKS) {
+ printf("Error: The number of size@base exceeds CONFIG_NR_DRAM_BANKS.\n");
+ return -EINVAL;
+ }
+
+ b = token;
+ s = strsep(&b, "@");
+ if (!s) {
+ printf("The format of jh_root_mem is size@base[,size@base...].\n");
+ return -EINVAL;
+ }
+ base[i] = simple_strtoull(b, NULL, 16);
+ size[i] = simple_strtoull(s, NULL, 16);
+ token = strtok(NULL, ",");
+ i++;
+ }
+
+ ret = fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+void board_quiesce_devices(void)
+{
+ int ret;
+ struct uclass *uc_dev;
+
+ ret = imx9_scmi_power_domain_enable(PD_HSIO_TOP, false);
+ if (ret) {
+ printf("%s: Failed for HSIO MIX: %d\n", __func__, ret);
+ return;
+ }
+
+ ret = imx9_scmi_power_domain_enable(PD_NETC, false);
+ if (ret) {
+ printf("%s: Failed for NETC MIX: %d\n", __func__, ret);
+ return;
+ }
+
+ ret = uclass_get(UCLASS_SPI_FLASH, &uc_dev);
+ if (uc_dev)
+ ret = uclass_destroy(uc_dev);
+ if (ret)
+ printf("couldn't remove SPI FLASH devices\n");
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+ return 0;
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env
new file mode 100644
index 00000000000..6ecaf9724c1
--- /dev/null
+++ b/board/nxp/imx952_evk/imx952_evk.env
@@ -0,0 +1,137 @@
+#ifdef CONFIG_ANDROID_SUPPORT
+splashpos=m,m
+splashimage=0x9FFF0000
+emmc_dev=0
+sd_dev=1
+#else
+
+#ifdef CONFIG_AHAB_BOOT
+sec_boot=yes
+#else
+sec_boot=no
+#endif
+
+jh_root_dtb=imx952-evk-root.dtb
+jh_mmcboot=setenv fdtfile ${jh_root_dtb};
+ setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe;
+ setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000;
+ if run loadimage; then
+ run mmcboot;
+ else run jh_netboot; fi;
+jh_netboot=setenv fdtfile ${jh_root_dtb};
+ setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000;
+ setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot;
+
+domu-android-auto=no
+xenhyper_bootargs=console=dtuart dom0_mem=4096M dom0_max_vcpus=2 pci-passthrough=on
+xenlinux_bootargs=
+xenlinux_console=hvc0 earlycon=xen
+xenlinux_addr=0x9c000000
+dom0fdt_file=CONFIG_DEFAULT_FDT_FILE
+xenboot_common=${get_cmd} ${loadaddr} xen;
+ ${get_cmd} ${fdt_addr} ${dom0fdt_file};
+ ${get_cmd} ${xenlinux_addr} ${image};
+ fdt addr ${fdt_addr};
+ fdt resize 256;
+ fdt mknode /chosen module@0;
+ fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>;
+ fdt set /chosen/module@0 bootargs "${bootargs} ${xenlinux_bootargs}";
+ fdt set /soc/bus@49000000/iommu@490d0000 status disabled;
+ fdt set /chosen/module@0 compatible "xen,linux-zimage" "xen,multiboot-module";
+ setenv bootargs ${xenhyper_bootargs};
+ booti ${loadaddr} - ${fdt_addr};
+xennetboot=setenv get_cmd dhcp;setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run netargs;run xenboot_common;
+xenmmcboot=setenv get_cmd "fatload mmc ${mmcdev}:${mmcpart}";setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run mmcargs;run xenboot_common;
+
+sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000; fdt addr ${fdt_addr_r};
+ fdt set /soc/bus@44000000/mailbox@445b0000/sram@445b1000/scmi-sram-section@0 reg <0x00000000 0x00000080>;
+ fdt rm /soc/mailbox@47530000;
+ fdt rm /soc/usb@4c010010;
+
+initrd_addr=0x93800000
+emmc_dev=0
+sd_dev=1
+scriptaddr=0x93500000
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+image=Image
+splashimage=0xA0000000
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x93000000
+fdt_addr=0x93000000
+cntr_addr=0xA8000000
+cntr_file=os_cntr_signed.bin
+boot_fit=no
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+bootm_size=0x10000000
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot}
+prepare_mcore=setenv mcore_args pd_ignore_unused;
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=booti ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r};
+mmcboot=echo Booting from mmc ...;
+ run mmcargs;
+ if test ${sec_boot} = yes; then
+ run auth_os;
+ else
+ if test ${boot_fit} = yes || test ${boot_fit} = try; then
+ bootm ${loadaddr};
+ else
+ if run loadfdt; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ fi;
+netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs
+ ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...;
+ run netargs;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ if test ${sec_boot} = yes; then
+ ${get_cmd} ${cntr_addr} ${cntr_file};
+ run auth_os;
+ else
+ ${get_cmd} ${loadaddr} ${image};
+ if test ${boot_fit} = yes || test ${boot_fit} = try; then
+ bootm ${loadaddr};
+ else
+ if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ fi;
+bsp_bootcmd=echo Running BSP bootcmd ...;
+ mmc dev ${mmcdev}; if mmc rescan; then
+ if run loadbootscript; then
+ run bootscript;
+ else
+ if test ${sec_boot} = yes; then
+ if run loadcntr; then
+ run mmcboot;
+ else run netboot;
+ fi;
+ else
+ if run loadimage; then
+ run mmcboot;
+ else run netboot;
+ fi;
+ fi;
+ fi;
+ fi;
+
+#endif
diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c
new file mode 100644
index 00000000000..d36c3a46b5e
--- /dev/null
+++ b/board/nxp/imx952_evk/spl.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#include <asm/arch/mu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/sections.h>
+#include <hang.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+ case USB_BOOT:
+ case USB2_BOOT:
+ return BOOT_DEVICE_BOARD;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_SPI;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void spl_board_init(void)
+{
+ int ret;
+
+ puts("Normal Boot\n");
+
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+}
+
+static void xspi_nor_reset(void)
+{
+ int ret;
+ struct gpio_desc desc;
+
+ ret = dm_gpio_lookup_name("GPIO5_11", &desc);
+ if (ret) {
+ printf("%s lookup GPIO5_11 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&desc, "XSPI_RST_B");
+ if (ret) {
+ printf("%s request XSPI_RST_B failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ /* assert the XSPI_RST_B */
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+ udelay(200); /* 50 ns at least, so use 200ns */
+ dm_gpio_set_value(&desc, 0); /* deassert the XSPI_RST_B */
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_SPL_RECOVER_DATA_SECTION
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ spl_save_restore_data();
+#endif
+
+ timer_init();
+
+ /* Need dm_init() to run before any SCMI calls can be made. */
+ spl_early_init();
+
+ /* Need enable SCMI drivers and ELE driver before enabling console */
+ ret = imx9_probe_mu();
+ if (ret)
+ hang(); /* if MU not probed, nothing can output, just hang here */
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ preloader_console_init();
+
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
+
+ get_reset_reason(true, false);
+
+ xspi_nor_reset();
+
+ board_init_r(NULL, 0);
+}
+
+#ifdef CONFIG_ANDROID_SUPPORT
+int board_get_emmc_id(void)
+{
+ return 0;
+}
+#endif
diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig
new file mode 100644
index 00000000000..59de9ee0333
--- /dev/null
+++ b/configs/imx952_evk_defconfig
@@ -0,0 +1,178 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x90200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SOURCE_FILE="imx952_evk"
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SF_DEFAULT_SPEED=200000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx952-evk"
+CONFIG_TARGET_IMX952_EVK=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0x20480000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x204d6000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x90400000
+CONFIG_SPL_OF_LIBFDT_ASSUME_MASK=0x0
+CONFIG_SPL=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y
+CONFIG_PCI=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_MEMTEST_START=0x90000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx952-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x30000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_CMD_OPTEE=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+# CONFIG_BOOTDEV_ETH is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_RX_ETH_BUFFER=8
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SPL_FIRMWARE=y
+# CONFIG_SCMI_AGENT_SMCCC is not set
+# CONFIG_SCMI_AGENT_OPTEE is not set
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_ADP5585_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_IMX_MU_MBOX=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_MII=y
+CONFIG_FSL_ENETC=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX_SCMI=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x90400000
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
diff --git a/doc/board/nxp/imx952_evk.rst b/doc/board/nxp/imx952_evk.rst
new file mode 100644
index 00000000000..9f20db2403f
--- /dev/null
+++ b/doc/board/nxp/imx952_evk.rst
@@ -0,0 +1,112 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx952_evk
+=======================
+
+U-Boot for the NXP i.MX952 15x15 LPDDR4X EVK board
+
+Quick Start
+-----------
+
+- Get ahab-container.img
+- Get DDR PHY Firmware Images
+- Get and Build OEI Images
+- Get and Build System Manager Image
+- Get and Build the ARM Trusted Firmware
+- Build the Bootloader Image
+- Boot
+
+Get ahab-container.img
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+
+.. code-block:: bash
+
+ $ wget https://nl2-nxrm.sw.nxp.com/repository/IMX_Yocto_Internal_Mirror_Recent/firmware-ele-imx-2.0.5-50c4793.bin
+ $ sh firmware-ele-imx-2.0.5-50c4793.bin --auto-accept
+ $ cp firmware-ele-imx-2.0.5-50c4793/mx952a0-ahab-container.img $(srctree)
+
+Get DDR PHY Firmware Images
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+
+.. code-block:: bash
+
+ $ wget https://nl2-nxrm.sw.nxp.com/repository/IMX_Yocto_Internal_Mirror_Recent/firmware-imx-8.32-c0491e4.bin
+ $ sh firmware-imx-8.32-c0491e4.bin --auto-accept
+ $ cp firmware-imx-8.32-c0491e4/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree)
+
+Get and Build OEI Images
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get OEI from: https://github.com/nxp-imx/imx-oei
+branch: lf-6.18.2-imx952-er1
+
+.. code-block:: bash
+
+ $ sudo apt -y install make gcc g++-multilib srecord
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz
+ $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz
+ $ export TOOLS=$PWD
+ $ git clone https://github.com/nxp-imx/imx-oei/ -b lf-6.18.2-imx952-er1
+ $ cd imx-oei
+ $ make board=mx952lp4x-15 oei=ddr DEBUG=1 all
+ $ cp build/mx952lp4x-15/ddr/oei-m33-ddr.bin $(srctree)
+
+Get and Build System Manager Image
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get System Manager from: https://github.com/nxp-imx/imx-sm
+branch: lf-6.18.2-imx952-er1
+
+.. code-block:: bash
+
+ $ sudo apt -y install make gcc g++-multilib srecord
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz
+ $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz
+ $ export TOOLS=$PWD
+ $ git clone https://github.com/nxp-imx/imx-sm/ -b lf-6.18.2-imx952-er1
+ $ cd imx-sm
+ $ make config=mx952evk all
+ $ cp build/mx952evk/m33_image.bin $(srctree)
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf-6.18.2-imx952-er1
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ unset LDFLAGS
+ $ unset AS
+ $ git clone https://github.com/nxp-imx/imx-atf/ -b lf-6.18.2-imx952-er1
+ $ cd imx-atf
+ $ make PLAT=imx952 bl31
+ $ cp build/imx952/release/bl31.bin $(srctree)
+
+Build the Bootloader Image
+--------------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx952_evk_defconfig
+ $ make
+
+Copy flash.bin to the MicroSD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
+
+Boot
+----
+
+Set i.MX952 boot device to MicroSD card
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index 01d3468a47d..8cd24aecf33 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -19,6 +19,7 @@ NXP Semiconductors
imx93_frdm
imx943_evk
imx95_evk
+ imx952_evk
imxrt1020-evk
imxrt1050-evk
imxrt1170-evk
diff --git a/include/configs/imx952_evk.h b/include/configs/imx952_evk.h
new file mode 100644
index 00000000000..dadc883027f
--- /dev/null
+++ b/include/configs/imx952_evk.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#ifndef __IMX952_EVK_H
+#define __IMX952_EVK_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_INIT_RAM_ADDR 0x90000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x90000000
+#define PHYS_SDRAM 0x90000000
+
+#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */
+#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */
+
+#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */
+#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000
+
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#ifdef CONFIG_ANDROID_SUPPORT
+#include "imx952_evk_android.h"
+#endif
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux
2026-02-05 13:55 ` [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux alice.guo
@ 2026-02-05 15:38 ` Tom Rini
2026-02-09 10:34 ` 回复: " Alice Guo (OSS)
0 siblings, 1 reply; 33+ messages in thread
From: Tom Rini @ 2026-02-05 15:38 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
[-- Attachment #1: Type: text/plain, Size: 1078 bytes --]
On Thu, Feb 05, 2026 at 09:55:16PM +0800, alice.guo@oss.nxp.com wrote:
> From: Alice Guo <alice.guo@nxp.com>
>
> Sync i.MX952 device tree files from linux-next next-20260202:
> - Add imx952.dtsi for SoC
> - Add imx952-evk.dts for i.MX952 EVK board
> - Add imx952-*.h headers for clock, pinctrl and power
>
> Imported from linux-next commit 193579fe0138 ("Add linux-next specific
> ifiles for 20260202")
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
> ---
> dts/upstream/src/arm64/freescale/imx952-clock.h | 215 ++++
> dts/upstream/src/arm64/freescale/imx952-evk.dts | 596 ++++++++++
> dts/upstream/src/arm64/freescale/imx952-pinfunc.h | 867 ++++++++++++++
> dts/upstream/src/arm64/freescale/imx952-power.h | 44 +
> dts/upstream/src/arm64/freescale/imx952.dtsi | 1266 +++++++++++++++++++++
> 5 files changed, 2988 insertions(+)
This needs to be done (as a series of, if needed)
tools/update-subtree.sh cherry-pick operations. That gives the right
commit message format that shows these are changes from upstream.
--
Tom
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support
2026-02-05 13:55 ` [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support alice.guo
@ 2026-02-05 15:45 ` Tom Rini
2026-02-06 1:24 ` Peng Fan
1 sibling, 0 replies; 33+ messages in thread
From: Tom Rini @ 2026-02-05 15:45 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
[-- Attachment #1: Type: text/plain, Size: 2897 bytes --]
On Thu, Feb 05, 2026 at 09:55:18PM +0800, alice.guo@oss.nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add support for i.MX952 15x15 lpddr4x board support.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
[snip]
> +void board_quiesce_devices(void)
> +{
> + int ret;
> + struct uclass *uc_dev;
> +
> + ret = imx9_scmi_power_domain_enable(PD_HSIO_TOP, false);
> + if (ret) {
> + printf("%s: Failed for HSIO MIX: %d\n", __func__, ret);
> + return;
> + }
> +
> + ret = imx9_scmi_power_domain_enable(PD_NETC, false);
> + if (ret) {
> + printf("%s: Failed for NETC MIX: %d\n", __func__, ret);
> + return;
> + }
> +
> + ret = uclass_get(UCLASS_SPI_FLASH, &uc_dev);
> + if (uc_dev)
> + ret = uclass_destroy(uc_dev);
> + if (ret)
> + printf("couldn't remove SPI FLASH devices\n");
> +}
Can we instead handle all of this via setting DM_FLAG_OS_PREPARE in
drivers as needed, so they're properly cleaned / released before OS
boot?
[snip]
> diff --git a/doc/board/nxp/imx952_evk.rst b/doc/board/nxp/imx952_evk.rst
> new file mode 100644
> index 00000000000..9f20db2403f
> --- /dev/null
> +++ b/doc/board/nxp/imx952_evk.rst
> @@ -0,0 +1,112 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +imx952_evk
> +=======================
This will be a doc warning and fail CI, please either push through CI or
build the docs locally (see doc/build/documentation.rst) with KDOC_WERROR=1
[snip]
> diff --git a/include/configs/imx952_evk.h b/include/configs/imx952_evk.h
> new file mode 100644
> index 00000000000..dadc883027f
> --- /dev/null
> +++ b/include/configs/imx952_evk.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2025-2026 NXP
> + */
> +
> +#ifndef __IMX952_EVK_H
> +#define __IMX952_EVK_H
> +
> +#include <linux/sizes.h>
> +#include <linux/stringify.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#define CFG_SYS_INIT_RAM_ADDR 0x90000000
> +#define CFG_SYS_INIT_RAM_SIZE 0x200000
> +
> +#define CFG_SYS_SDRAM_BASE 0x90000000
> +#define PHYS_SDRAM 0x90000000
> +
> +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */
> +#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */
> +
> +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */
> +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000
> +
> +#define WDOG_BASE_ADDR WDG3_BASE_ADDR
> +
> +#ifdef CONFIG_ANDROID_SUPPORT
> +#include "imx952_evk_android.h"
> +#endif
It's a really bad idea having the board.h file bring in other includes.
We aren't using SZ macros, and a patch to clean up WDOG_BASE_ADDR so it
doesn't need to be in the board.h would be a good cleanup to do, but
maybe for now just make sure the watchdog driver has the regs header
included?
--
Tom
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API
2026-02-05 13:55 ` [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API alice.guo
@ 2026-02-06 0:34 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:34 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:07PM +0800, alice.guo@oss.nxp.com wrote:
>From: Ye Li <ye.li@nxp.com>
>
>SM has implemented MISC protocol for get DDR info. Using this API, u-boot
>could get DDR size instead of static configs. This will facilitate the DDR
>ECC enabled case which has 1/8 DDR size reserved by ECC data. SM get DDR info
>API provides the reduced DDR size.
>To be compatible with old SM, if calling this API failed, will fall back
>to static configs.
>
>Signed-off-by: Ye Li <ye.li@nxp.com>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/include/asm/mach-imx/sys_proto.h | 10 ++++
> arch/arm/mach-imx/imx9/scmi/soc.c | 76 +++++++++++++++++++++++++------
> include/scmi_protocols.h | 3 +-
> 3 files changed, 74 insertions(+), 15 deletions(-)
>
>diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
>index 46da7a1eff5..6c8bd6c9085 100644
>--- a/arch/arm/include/asm/mach-imx/sys_proto.h
>+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
>@@ -254,6 +254,16 @@ struct scmi_rom_passover_get_out {
> u32 passover[(sizeof(rom_passover_t) + 8) / 4];
> };
>
>+struct scmi_ddr_info_out {
>+ s32 status;
>+ u32 attributes;
>+ u32 mts;
>+ u32 startlow;
>+ u32 starthigh;
>+ u32 endlow;
>+ u32 endhigh;
>+};
Add comment to explain the fields of the structure.
>+
> #endif
>
> /* For i.MX ULP */
>diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
>index c1458ccca3c..e573736825c 100644
>--- a/arch/arm/mach-imx/imx9/scmi/soc.c
>+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
>@@ -58,6 +58,35 @@ uint32_t scmi_get_rom_data(rom_passover_t *rom_data)
> return 0;
> }
>
>+int scmi_misc_ddrinfo(u32 ddrc_id, struct scmi_ddr_info_out *out)
>+{
>+ u32 in = ddrc_id;
>+ struct scmi_msg msg = {
>+ .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC,
>+ .message_id = SCMI_MISC_DDR_INFO_GET,
>+ .in_msg = (u8 *)&in,
>+ .in_msg_sz = sizeof(in),
>+ .out_msg = (u8 *)out,
>+ .out_msg_sz = sizeof(*out),
>+ };
>+ int ret;
>+ struct udevice *dev;
>+
>+ memset(out, 0, sizeof(*out));
This could be done in caller by set an initialization value to 0.
>+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
>+ if (ret)
>+ return ret;
>+
>+ ret = devm_scmi_process_msg(dev, &msg);
>+ if (ret != 0 || out->status != 0) {
>+ printf("Failed to get ddr cfg, scmi_err = %d\n",
>+ out->status);
>+ return -EINVAL;
>+ }
>+
>+ return 0;
>+}
>+
> #if IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
> __weak int board_mmc_get_env_dev(int devno)
> {
>@@ -335,25 +364,44 @@ void enable_caches(void)
>
> __weak int board_phys_sdram_size(phys_size_t *size)
> {
>+ struct scmi_ddr_info_out ddr_info;
Init with "= { 0 }"
>+ int ret;
>+ u32 ddrc_id = 0, ddrc_num = 1;
> phys_size_t start, end;
>- phys_size_t val;
>
> if (!size)
> return -EINVAL;
>
>- val = readl(REG_DDR_CS0_BNDS);
>- start = (val >> 16) << 24;
>- end = (val & 0xFFFF);
>- end = end ? end + 1 : 0;
>- end = end << 24;
>- *size = end - start;
>-
>- val = readl(REG_DDR_CS1_BNDS);
>- start = (val >> 16) << 24;
>- end = (val & 0xFFFF);
>- end = end ? end + 1 : 0;
>- end = end << 24;
>- *size += end - start;
>+ *size = 0;
>+ do {
>+ ret = scmi_misc_ddrinfo(ddrc_id++, &ddr_info);
>+ if (ret) {
>+ /* if get DDR info failed, fall to default config */
>+ *size = PHYS_SDRAM_SIZE;
>+#ifdef PHYS_SDRAM_2_SIZE
>+ *size += PHYS_SDRAM_2_SIZE;
>+#endif
You dropped the method of directly reading REG_DDR_CS[0,1]_BNDS but switch
to using PHYS_SDRAM[x]_SIZE, and commit log does not mention it.
>+ return 0;
>+ } else {
>+ ddrc_num = ((ddr_info.attributes >> 16) & 0x3);
>+ start = ddr_info.starthigh;
>+ start <<= 32;
>+ start += ddr_info.startlow;
>+
>+ end = ddr_info.endhigh;
>+ end <<= 32;
>+ end += ddr_info.endlow;
>+
>+ *size += end + 1 - start;
>+
>+ debug("ddr info attr 0x%x, start 0x%x 0x%x, end 0x%x 0x%x, mts %u\n",
>+ ddr_info.attributes, ddr_info.starthigh, ddr_info.startlow,
>+ ddr_info.endhigh, ddr_info.endlow, ddr_info.mts);
>+ }
>+ } while (ddrc_id < ddrc_num);
>+
>+ /* SM reports total DDR size, need remove secure memory */
>+ *size -= PHYS_SDRAM - 0x80000000;
secure memory size is 2GB? Need to mention in commit log or at the place
of struct scmi_ddr_info_out definition about this behavior.
Regards
Peng
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 02/12] imx95/imx94: Remove board_phys_sdram_size from each board
2026-02-05 13:55 ` [PATCH v1 02/12] imx95/imx94: Remove board_phys_sdram_size from each board alice.guo
@ 2026-02-06 0:35 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:35 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:08PM +0800, alice.guo@oss.nxp.com wrote:
>From: Ye Li <ye.li@nxp.com>
>
>Change to use default board_phys_sdram_size implementation in soc.c,
>which will call SM API to get DDR size.
>
>If board has special implementation for DDR size, then board_phys_sdram_size
>could be implemented in board file to override the default one in soc.c.
>
>Signed-off-by: Ye Li <ye.li@nxp.com>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 03/12] pinctrl: nxp: Add i.MX952 support
2026-02-05 13:55 ` [PATCH v1 03/12] pinctrl: nxp: Add i.MX952 support alice.guo
@ 2026-02-06 0:36 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:36 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:09PM +0800, alice.guo@oss.nxp.com wrote:
>From: Ye Li <ye.li@nxp.com>
>
>Multiple pads can drive the same module input pin, and a daisy chain
>register is used to select the active input path. This patch defines
>DAISY_OFFSET_IMX952 (0x460) and allows binding on i.MX952.
>
>Signed-off-by: Ye Li <ye.li@nxp.com>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 04/12] arm: imx: Add i.MX952 CPU type support
2026-02-05 13:55 ` [PATCH v1 04/12] arm: imx: Add i.MX952 CPU type support alice.guo
@ 2026-02-06 0:37 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:37 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:10PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Add CPU type definition and detection macro for i.MX952 SoC.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 05/12] imx: ele_ahab: Add i.MX952 support to display_life_cycle()
2026-02-05 13:55 ` [PATCH v1 05/12] imx: ele_ahab: Add i.MX952 support to display_life_cycle() alice.guo
@ 2026-02-06 0:38 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:38 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:11PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Extend display_life_cycle() to support i.MX952.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 06/12] imx: container: Add i.MX952 support to get_imageset_end()
2026-02-05 13:55 ` [PATCH v1 06/12] imx: container: Add i.MX952 support to get_imageset_end() alice.guo
@ 2026-02-06 0:40 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:40 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:12PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Extend get_imageset_end() to handle i.MX952.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions
2026-02-05 13:55 ` [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions alice.guo
@ 2026-02-06 0:41 ` Peng Fan
2026-02-06 3:59 ` Fabio Estevam
1 sibling, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:41 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:13PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Add WDG3, WDG4 and WDG5 base addresses for i.MX952.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support
2026-02-05 13:55 ` [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support alice.guo
@ 2026-02-06 0:45 ` Peng Fan
2026-02-22 1:34 ` David Zang
1 sibling, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:45 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:14PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Add basic SoC support for i.MX952:
>- Add CONFIG_IMX952 Kconfig option
>- Include i.MX952 clock and power headers
>- Set CPU speed grade to 1.7GHz for i.MX952
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 09/12] cpu: imx952: Add i.MX952 support
2026-02-05 13:55 ` [PATCH v1 09/12] cpu: imx952: Add i.MX952 support alice.guo
@ 2026-02-06 0:46 ` Peng Fan
0 siblings, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:46 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:15PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>This patch is used to add the imx type string of i.MX952 ao that the
ao->so
>i.MX952 CPU info can be printed.
>
Regards,
Peng
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK
2026-02-05 13:55 ` [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK alice.guo
@ 2026-02-06 0:51 ` Peng Fan
2026-02-06 1:27 ` Tom Rini
0 siblings, 1 reply; 33+ messages in thread
From: Peng Fan @ 2026-02-06 0:51 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:17PM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Add U-Boot specific device tree configuration for i.MX952 EVK board.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/dts/imx952-evk-u-boot.dtsi | 58 +++++++
> arch/arm/dts/imx952-u-boot.dtsi | 327 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 385 insertions(+)
>
>diff --git a/arch/arm/dts/imx952-evk-u-boot.dtsi b/arch/arm/dts/imx952-evk-u-boot.dtsi
>new file mode 100644
>index 00000000000..1b2c314a41b
>--- /dev/null
>+++ b/arch/arm/dts/imx952-evk-u-boot.dtsi
>@@ -0,0 +1,58 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2026 NXP
>+ */
>+
>+#include "imx952-u-boot.dtsi"
>+
>+&i2c3_pcal6408 {
>+ compatible = "ti,tca6408";
>+ label = "i2c3_io";
>+};
>+
>+&i2c4_pcal6408 {
>+ compatible = "ti,tca6408";
>+ label = "i2c4_io";
>+};
>+
>+&pcal6416 {
>+ compatible = "ti,tca6416";
>+ label = "i2c6_io";
>+};
>+
>+&pcal6524 {
>+ label = "i2c7_io";
>+};
>+
>+&usb1 {
>+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
>+ /delete-property/power-domains;
>+ bootph-pre-ram;
>+ extcon = <&ptn5110>;
>+};
>+
>+&usb2 {
>+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
>+ /delete-property/power-domains;
>+ bootph-pre-ram;
>+};
>+
>+&usbmisc1 {
>+ bootph-pre-ram;
>+};
>+
>+&usbmisc2 {
>+ bootph-pre-ram;
>+};
>+
>+&usbphynop1 {
>+ bootph-pre-ram;
>+};
>+
>+&usbphynop2 {
>+ bootph-pre-ram;
>+};
>+
>+&wdog3 {
>+ status = "disabled";
>+};
>diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi
>new file mode 100644
>index 00000000000..208931ba884
>--- /dev/null
>+++ b/arch/arm/dts/imx952-u-boot.dtsi
>@@ -0,0 +1,327 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2026 NXP
>+ */
>+
>+/ {
>+ binman {
>+ multiple-images;
>+
>+ m33-oei-ddrfw {
>+ pad-byte = <0x00>;
>+ align-size = <0x8>;
>+ filename = "m33-oei-ddrfw.bin";
>+
>+ oei-m33-ddr {
>+ align-size = <0x4>;
>+ filename = "oei-m33-ddr.bin";
>+ type = "blob-ext";
>+ };
>+
>+ imx-lpddr {
>+ type = "nxp-header-ddrfw";
>+
>+ imx-lpddr-imem {
>+ filename = "lpddr4x_imem_v202409.bin";
>+ type = "blob-ext";
>+ };
>+
>+ imx-lpddr-dmem {
>+ filename = "lpddr4x_dmem_v202409.bin";
>+ type = "blob-ext";
>+ };
>+ };
>+
>+ imx-lpddr-qb {
>+ type = "nxp-header-ddrfw";
>+
>+ imx-lpddr-imem-qb {
>+ filename = "lpddr4x_imem_qb_v202409.bin";
>+ type = "blob-ext";
>+ };
>+
>+ imx-lpddr-dmem-qb {
>+ filename = "lpddr4x_dmem_qb_v202409.bin";
>+ type = "blob-ext";
>+ };
>+ };
>+ };
>+
>+ imx-boot {
>+ filename = "flash.bin";
>+ pad-byte = <0x00>;
>+
>+ spl {
>+ type = "nxp-imx9image";
>+ cfg-path = "spl/u-boot-spl.cfgout";
>+ args;
>+
>+ cntr-version = <2>;
>+ boot-from = "sd";
>+ soc-type = "IMX9";
>+ append = "mx952a0-ahab-container.img";
>+ container;
>+ dummy-ddr;
>+ image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
>+ hold = <0x10000>;
>+ image1 = "m33", "m33_image.bin", "0x1ffc0000";
>+ image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
>+ dummy-v2x = <0x8b000000>;
>+ };
>+
>+ u-boot {
>+ type = "nxp-imx9image";
>+ cfg-path = "u-boot-container.cfgout";
>+ args;
>+
>+ cntr-version = <2>;
>+ boot-from = "sd";
>+ soc-type = "IMX9";
>+ container;
>+ image0 = "a55", "bl31.bin", "0x8a200000";
>+ image1 = "a55", "u-boot.bin", "0x90200000";
>+ };
>+ };
>+ };
>+
>+ chosen {
>+ bootargs = "console=ttyLP0,115200 earlycon";
>+ };
>+
>+ aliases {
>+ usb_gadget0 = &usbg1;
>+ usb_gadget1 = &usbg2;
>+ };
>+
>+ usbg1: usbg1 {
>+ compatible = "fsl,imx27-usb-gadget";
>+ dr_mode = "peripheral";
>+ chipidea,usb = <&usb1>;
>+ bootph-pre-ram;
>+ status = "okay";
>+ };
>+
>+ usbg2: usbg2 {
>+ compatible = "fsl,imx27-usb-gadget";
>+ dr_mode = "peripheral";
>+ chipidea,usb = <&usb2>;
>+ bootph-pre-ram;
>+ status = "okay";
>+ };
The above two nodes does not have a working driver in upstream.
>+
>+ reg_m2_pwr: regulator-m2-pwr {
>+ compatible = "regulator-fixed";
>+ regulator-name = "M.2-power";
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
>+ enable-active-high;
>+ /*
>+ * M.2 device only can be enabled(W_DISABLE1#) after all Power
>+ * Rails reach their minimum operating voltage (PCI Express M.2
>+ * Specification r5.1 3.1.4 Power-up Timing).
>+ * Set a delay equal to the max value of Tsettle here.
>+ */
>+ startup-delay-us = <5000>;
>+ };
>+};
>+
>+&A55_0 {
>+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
>+ /delete-property/ power-domains;
>+};
>+
>+&A55_1 {
>+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
>+ /delete-property/ power-domains;
>+};
>+
>+&A55_2 {
>+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
>+ /delete-property/ power-domains;
>+};
>+
>+&A55_3 {
>+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
>+ /delete-property/ power-domains;
>+};
>+
>+&aips1 {
>+ bootph-all;
>+};
>+
>+&aips2 {
>+ bootph-all;
>+};
>+
>+&aips3 {
>+ bootph-all;
>+};
>+
>+&clk_ext1 {
>+ bootph-all;
>+};
>+
>+&clk_dummy {
>+ bootph-all;
>+};
>+
>+&clk_osc_24m {
>+ bootph-all;
>+};
>+
>+&elemu1 {
>+ status = "okay";
>+ bootph-all;
>+};
>+
>+&elemu3 {
>+ status = "okay";
>+ bootph-all;
>+};
>+
>+&{/firmware} {
>+ bootph-all;
>+};
>+
>+&{/firmware/scmi} {
>+ bootph-all;
>+};
>+
>+&{/firmware/scmi/protocol@11} {
>+ bootph-all;
>+};
>+
>+&{/firmware/scmi/protocol@13} {
>+ bootph-all;
>+};
>+
>+&{/firmware/scmi/protocol@14} {
>+ bootph-all;
>+};
>+
>+&{/firmware/scmi/protocol@15} {
>+ bootph-all;
>+};
>+
>+&{/firmware/scmi/protocol@19} {
>+ bootph-all;
>+};
>+
>+&gpio1 {
>+ reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
>+};
>+
>+&gpio2 {
>+ reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>;
>+ bootph-pre-ram;
>+ /*
>+ * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2
>+ * is assigned to M7, disable gpio2 here
>+ */
>+ status = "disabled";
>+};
>+
>+&gpio3 {
>+ reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>;
>+ bootph-pre-ram;
>+};
>+
>+&gpio4 {
>+ reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>;
>+ bootph-pre-ram;
>+};
>+
>+&gpio5 {
>+ reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>;
>+ bootph-pre-ram;
>+};
>+
>+&lpuart1 {
>+ bootph-pre-ram;
>+};
>+
>+&mu2 {
>+ bootph-all;
>+};
>+
>+®_usdhc2_vmmc {
>+ bootph-pre-ram;
>+};
>+
>+&scmi_buf0 {
>+ reg = <0x0 0x400>;
>+ bootph-all;
>+};
>+
>+&scmi_buf1 {
>+ bootph-all;
>+};
>+
>+&{/soc} {
>+ bootph-all;
>+};
>+
>+&sram0 {
>+ bootph-all;
>+};
>+
>+&usdhc1 {
>+ bootph-pre-ram;
>+};
>+
>+&usdhc2 {
>+ bootph-pre-ram;
>+};
>+
>+&scmi_iomuxc {
>+ pinctrl-names = "default";
>+ pinctrl-0 = <&pinctrl_hog>;
>+
>+ pinctrl_hog: hoggrp {
>+ bootph-pre-ram;
>+
>+ fsl,pins = <
>+ IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x3fe
>+ IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e
>+ IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x3fe
>+ IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x3fe
>+ >;
Add a comment for the settings, why they needs to be set in hog.
>+ };
>+};
>+
>+&pinctrl_uart1 {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc1 {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc1_100mhz {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc1_200mhz {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc2 {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc2_100mhz {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc2_200mhz {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_usdhc2_gpio {
>+ bootph-pre-ram;
>+};
>+
>+&pinctrl_reg_usdhc2_vmmc {
>+ bootph-pre-ram;
>+};
Regards
Peng
>
>--
>2.43.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support
2026-02-05 13:55 ` [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support alice.guo
2026-02-05 15:45 ` Tom Rini
@ 2026-02-06 1:24 ` Peng Fan
1 sibling, 0 replies; 33+ messages in thread
From: Peng Fan @ 2026-02-06 1:24 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 05, 2026 at 09:55:18PM +0800, alice.guo@oss.nxp.com wrote:
>From: Peng Fan <peng.fan@nxp.com>
>
>Add support for i.MX952 15x15 lpddr4x board support.
>
>Signed-off-by: Peng Fan <peng.fan@nxp.com>
>Signed-off-by: Ye Li <ye.li@nxp.com>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/mach-imx/Makefile | 2 +-
> arch/arm/mach-imx/imx9/Kconfig | 14 ++
> board/nxp/imx952_evk/Kconfig | 12 ++
> board/nxp/imx952_evk/MAINTAINERS | 6 +
> board/nxp/imx952_evk/Makefile | 14 ++
> board/nxp/imx952_evk/imx952_evk.c | 297 ++++++++++++++++++++++++++++++++++++
> board/nxp/imx952_evk/imx952_evk.env | 137 +++++++++++++++++
> board/nxp/imx952_evk/spl.c | 115 ++++++++++++++
> configs/imx952_evk_defconfig | 178 +++++++++++++++++++++
> doc/board/nxp/imx952_evk.rst | 112 ++++++++++++++
> doc/board/nxp/index.rst | 1 +
> include/configs/imx952_evk.h | 31 ++++
> 12 files changed, 918 insertions(+), 1 deletion(-)
>
>diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>index 0f6e737c0b9..bf6820de655 100644
>--- a/arch/arm/mach-imx/Makefile
>+++ b/arch/arm/mach-imx/Makefile
>@@ -223,7 +223,7 @@ endif
>
> ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
>
>-ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),)
>+ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94),$(CONFIG_IMX952))),)
> SPL: spl/u-boot-spl.bin FORCE
> $(call if_changed,mkimage)
>
>diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
>index 716940930a6..2ba088c49c5 100644
>--- a/arch/arm/mach-imx/imx9/Kconfig
>+++ b/arch/arm/mach-imx/imx9/Kconfig
>@@ -162,6 +162,19 @@ config TARGET_TORADEX_SMARC_IMX95
> bool "Support Toradex SMARC iMX95"
> select IMX95
>
>+config TARGET_IMX952_EVK
>+ bool "imx952_evk"
>+ select CMD_REMOTEPROC
>+ select IMX_SM_CPU
>+ select IMX_SM_LMM
>+ select IMX952
>+ select REMOTEPROC_IMX
>+ select REGMAP
>+ select SYSCON
Move the remoteproc related to defconfig.
>+ imply BOOTSTD_BOOTCOMMAND
>+ imply BOOTSTD_FULL
>+ imply OF_UPSTREAM
>+
> endchoice
>
> source "board/nxp/imx91_evk/Kconfig"
>@@ -175,5 +188,6 @@ source "board/variscite/imx93_var_som/Kconfig"
> source "board/nxp/imx94_evk/Kconfig"
> source "board/nxp/imx95_evk/Kconfig"
> source "board/toradex/smarc-imx95/Kconfig"
>+source "board/nxp/imx952_evk/Kconfig"
>
> endif
>diff --git a/board/nxp/imx952_evk/Kconfig b/board/nxp/imx952_evk/Kconfig
>new file mode 100644
>index 00000000000..96f01323aca
>--- /dev/null
>+++ b/board/nxp/imx952_evk/Kconfig
>@@ -0,0 +1,12 @@
>+if TARGET_IMX952_EVK
>+
>+config SYS_BOARD
>+ default "imx952_evk"
>+
>+config SYS_VENDOR
>+ default "nxp"
>+
>+config SYS_CONFIG_NAME
>+ default "imx952_evk"
>+
>+endif
>diff --git a/board/nxp/imx952_evk/MAINTAINERS b/board/nxp/imx952_evk/MAINTAINERS
>new file mode 100644
>index 00000000000..cc004f9467e
>--- /dev/null
>+++ b/board/nxp/imx952_evk/MAINTAINERS
>@@ -0,0 +1,6 @@
>+i.MX952 EVK BOARD
>+M: Alice Guo <alice.guo@nxp.com>
>+S: Maintained
>+F: board/nxp/imx952_evk/
>+F: include/configs/imx952_evk.h
>+F: configs/imx952_evk_defconfig
>diff --git a/board/nxp/imx952_evk/Makefile b/board/nxp/imx952_evk/Makefile
>new file mode 100644
>index 00000000000..1581721dc78
>--- /dev/null
>+++ b/board/nxp/imx952_evk/Makefile
>@@ -0,0 +1,14 @@
>+#
>+# Copyright 2025-2026 NXP
>+#
>+# SPDX-License-Identifier: GPL-2.0+
>+#
>+
>+# Add include path for NXP device tree header files from Linux.
>+ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/
>+
>+obj-y += imx952_evk.o
>+
>+ifdef CONFIG_SPL_BUILD
>+obj-y += spl.o
>+endif
>diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c
>new file mode 100644
>index 00000000000..8b4b2083a20
>--- /dev/null
>+++ b/board/nxp/imx952_evk/imx952_evk.c
>@@ -0,0 +1,297 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2025-2026 NXP
>+ */
>+
>+#include <asm/arch/clock.h>
>+#include <asm/arch/sys_proto.h>
>+#include <asm/gpio.h>
>+#include <dm/uclass.h>
>+#include <dm/uclass-internal.h>
>+#include <env.h>
>+#include <fdt_support.h>
>+#include <imx952-power.h>
>+#include <init.h>
>+#include <linux/delay.h>
>+#include <power/regulator.h>
>+#include <scmi_agent.h>
>+#include <usb.h>
sort the headers.
Generic headers
asm/headers
asm/arch/headers
asm/mach/headers
>+
>+#define PD_HSIO_TOP IMX952_PD_HSIO_TOP
>+#define PD_NETC IMX952_PD_NETC
>+#define PD_DISPLAY IMX952_PD_DISPLAY
>+#define PD_CAMERA IMX952_PD_CAMERA
Use tab to align the macros.
>+
>+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
>+#define IMX_BOOT_IMAGE_GUID \
>+ EFI_GUID(0x58a661f3, 0xe7c7, 0x4173, 0x80, 0x21, \
>+ 0xa3, 0x1b, 0x95, 0xc8, 0x6e, 0x9b)
>+
>+struct efi_fw_image fw_images[] = {
>+ {
>+ .image_type_id = IMX_BOOT_IMAGE_GUID,
>+ .fw_name = u"IMX952-EVK-RAW",
>+ .image_index = 1,
>+ },
>+};
>+
>+struct efi_capsule_update_info update_info = {
>+ .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1",
>+ .num_images = ARRAY_SIZE(fw_images),
>+ .images = fw_images,
>+};
>+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
>+
>+int board_early_init_f(void)
>+{
>+ /* UART1: A55, UART2: M33, UART3: M7 */
>+ init_uart_clk(0);
Drop this. no need.
>+
>+ return 0;
>+}
>+
>+#ifdef CONFIG_USB_TCPC
>+struct tcpc_port port;
>+struct tcpc_port_config port_config = {
>+ .i2c_bus = 6, /* i2c7 */
>+ .addr = 0x50,
>+ .port_type = TYPEC_PORT_DRP,
>+ .disable_pd = true,
>+};
>+
>+static int setup_typec(void)
>+{
>+ int ret;
>+
>+ debug("tcpc_init port 1\n");
>+ ret = tcpc_init(&port, port_config, NULL);
>+ if (ret) {
>+ printf("%s: tcpc port init failed, err=%d\n",
>+ __func__, ret);
>+ }
>+
>+ return ret;
>+}
>+#endif
Drop the tcpc part. this is not supported in upstream.
>+
>+static int imx9_scmi_power_domain_enable(u32 domain, bool enable)
>+{
>+ struct udevice *dev;
>+ int ret;
>+
>+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
>+ if (ret)
>+ return ret;
>+
>+ return scmi_pwd_state_set(dev, 0, domain, enable ? 0 : BIT(30));
>+}
>+
>+int board_usb_init(int index, enum usb_init_type init)
>+{
>+ int ret = 0;
>+
>+ if (index == 0 && init == USB_INIT_DEVICE) {
>+ ret = imx9_scmi_power_domain_enable(PD_HSIO_TOP, true);
>+ if (ret) {
>+ printf("SCMI_POWWER_STATE_SET Failed for USB\n");
>+ return ret;
>+ }
>+ } else if (index == 0 && init == USB_INIT_HOST) {
>+ return ret;
>+ }
>+
>+ return 0;
>+}
>+
>+int board_usb_cleanup(int index, enum usb_init_type init)
>+{
>+ int ret = 0;
>+
>+ if (index == 0 && init == USB_INIT_HOST) {
>+#ifdef CONFIG_USB_TCPC
>+ ret = tcpc_disable_src_vbus(&port);
>+#endif
>+ }
>+
>+ return ret;
>+}
Drop the tcpc part. one more question, does the usb host and gadget both
work?
>+
>+static void netc_phy_rst(const char *gpio_name, const char *label)
>+{
>+ int ret;
>+ struct gpio_desc desc;
>+
>+ /* ENET_RST_B */
>+ ret = dm_gpio_lookup_name(gpio_name, &desc);
>+ if (ret) {
>+ printf("%s lookup %s failed ret = %d\n", __func__, gpio_name, ret);
>+ return;
>+ }
>+
>+ ret = dm_gpio_request(&desc, label);
>+ if (ret) {
>+ printf("%s request %s failed ret = %d\n", __func__, label, ret);
>+ return;
>+ }
>+
>+ /* assert the ENET_RST_B */
>+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
>+ udelay(10000);
>+ dm_gpio_set_value(&desc, 0); /* deassert the ENET_RST_B */
>+ udelay(80000);
>+}
>+
>+void netc_init(void)
>+{
>+ int ret;
>+
>+ ret = imx9_scmi_power_domain_enable(PD_NETC, false);
error check is not added.
>+ udelay(10000);
>+
>+ /* Power up the NETC MIX. */
>+ ret = imx9_scmi_power_domain_enable(PD_NETC, true);
An comment is required on why power down , then power up again.
>+ if (ret) {
>+ printf("SCMI_POWWER_STATE_SET Failed for NETC MIX\n");
>+ return;
>+ }
>+
>+ netc_phy_rst("i2c6_io@21_13", "ENET1_RST_B");
This is not good to put here. Could phy rst be done in drivers?
>+
>+ pci_init();
>+}
>+
>+static void pcie_setup(void)
>+{
>+ int ret;
>+ struct udevice *dev;
>+
>+ ret = regulator_get_by_devname("regulator-m2-pwr", &dev);
>+ if (ret) {
>+ printf("Get regulator-m2-pwr regulator failed %d\n", ret);
>+ return;
>+ }
>+
>+ ret = regulator_set_enable_if_allowed(dev, true);
>+ if (ret) {
>+ printf("Enable regulator-m2-pwr regulator %d\n", ret);
>+ return;
>+ }
>+}
>+
>+void lvds_backlight_on(void)
>+{
>+ /* None */
>+}
Drop.
Two much code added from downstream. Please cleanup this patch
to make it as i.MX95/4 EVK board code.
Then add more features step by step.
Regards
Peng
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK
2026-02-06 0:51 ` Peng Fan
@ 2026-02-06 1:27 ` Tom Rini
0 siblings, 0 replies; 33+ messages in thread
From: Tom Rini @ 2026-02-06 1:27 UTC (permalink / raw)
To: Peng Fan
Cc: alice.guo, NXP i.MX U-Boot Team, u-boot, Stefano Babic,
Fabio Estevam, Peng Fan, Ye Li, Jindong Yue, Jacky Bai,
Marek Vasut, Rasmus Villemoes, Fedor Ross,
João Paulo Gonçalves, Patrice Chotard, Valentin Caron,
Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan, Ji Luo,
Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf, David Zang,
Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo, Tim Harvey,
Alice Guo
[-- Attachment #1: Type: text/plain, Size: 428 bytes --]
On Fri, Feb 06, 2026 at 08:51:28AM +0800, Peng Fan wrote:
> On Thu, Feb 05, 2026 at 09:55:17PM +0800, alice.guo@oss.nxp.com wrote:
> >From: Alice Guo <alice.guo@nxp.com>
> >
> >Add U-Boot specific device tree configuration for i.MX952 EVK board.
> >
> >Signed-off-by: Alice Guo <alice.guo@nxp.com>
[snip]
> >+&usbmisc1 {
> >+ bootph-pre-ram;
> >+};
I forgot earlier, here and elsewhere, upstream this.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions
2026-02-05 13:55 ` [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions alice.guo
2026-02-06 0:41 ` Peng Fan
@ 2026-02-06 3:59 ` Fabio Estevam
2026-02-09 10:24 ` 回复: " Alice Guo (OSS)
1 sibling, 1 reply; 33+ messages in thread
From: Fabio Estevam @ 2026-02-06 3:59 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Tom Rini, Peng Fan,
Ye Li, Jindong Yue, Jacky Bai, Marek Vasut, Rasmus Villemoes,
Fedor Ross, João Paulo Gonçalves, Patrice Chotard,
Valentin Caron, Vinh Nguyen, Sam Protsenko, Ranjani Vaidyanathan,
Ji Luo, Frank Li, Sumit Garg, Adam Ford, Frieder Schrempf,
David Zang, Andrew Goodbody, Sumit Garg, Marek Vasut, Joseph Guo,
Tim Harvey, Alice Guo
Hi Alice,
On Thu, Feb 5, 2026 at 12:16 PM <alice.guo@oss.nxp.com> wrote:
>
> From: Alice Guo <alice.guo@nxp.com>
>
> Add WDG3, WDG4 and WDG5 base addresses for i.MX952.
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
> ---
> arch/arm/include/asm/arch-imx9/imx-regs.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
> index 2d084e5227a..7c7a34f74af 100644
> --- a/arch/arm/include/asm/arch-imx9/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
> @@ -17,6 +17,11 @@
>
> #define ANATOP_BASE_ADDR 0x44480000UL
>
> +#ifdef CONFIG_IMX952
> +#define WDG3_BASE_ADDR 0x420b0000UL
> +#define WDG4_BASE_ADDR 0x420c0000UL
> +#define WDG5_BASE_ADDR 0x420d0000UL
> +#else
> #ifdef CONFIG_IMX94
> #define WDG3_BASE_ADDR 0x49220000UL
> #define WDG4_BASE_ADDR 0x49230000UL
> @@ -25,6 +30,7 @@
> #define WDG4_BASE_ADDR 0x424a0000UL
> #endif
> #define WDG5_BASE_ADDR 0x424b0000UL
> +#endif
Can we improve this and retrieve the watchdog base address from the devicetree?
^ permalink raw reply [flat|nested] 33+ messages in thread
* 回复: [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions
2026-02-06 3:59 ` Fabio Estevam
@ 2026-02-09 10:24 ` Alice Guo (OSS)
2026-02-09 11:21 ` Fabio Estevam
0 siblings, 1 reply; 33+ messages in thread
From: Alice Guo (OSS) @ 2026-02-09 10:24 UTC (permalink / raw)
To: Fabio Estevam, Alice Guo (OSS)
Cc: dl-uboot-imx, u-boot@lists.denx.de, Stefano Babic, Tom Rini,
Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Ross, Fedor, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, tharvey@gateworks.com, Alice Guo
> -----邮件原件-----
> 发件人: Fabio Estevam <festevam@gmail.com>
> 发送时间: 2026年2月6日 11:59
> 收件人: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> 抄送: dl-uboot-imx <uboot-imx@nxp.com>; u-boot@lists.denx.de; Stefano
> Babic <sbabic@nabladev.com>; Tom Rini <trini@konsulko.com>; Peng Fan
> <peng.fan@nxp.com>; Ye Li <ye.li@nxp.com>; Jindong Yue
> <jindong.yue@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Marek Vasut
> <marek.vasut+renesas@mailbox.org>; Rasmus Villemoes <ravi@prevas.dk>;
> Ross, Fedor <fedor.ross@ifm.com>; João Paulo Gonçalves
> <joao.goncalves@toradex.com>; Patrice Chotard
> <patrice.chotard@foss.st.com>; Valentin Caron <valentin.caron@foss.st.com>;
> Vinh Nguyen <vinh.nguyen.xz@renesas.com>; Sam Protsenko
> <semen.protsenko@linaro.org>; Ranjani Vaidyanathan
> <ranjani.vaidyanathan@nxp.com>; Ji Luo <ji.luo@nxp.com>; Frank Li
> <frank.li@nxp.com>; Sumit Garg <sumit.garg@oss.qualcomm.com>; Adam
> Ford <aford173@gmail.com>; Frieder Schrempf
> <frieder.schrempf@kontron.de>; David Zang <davidzangcs@gmail.com>;
> Andrew Goodbody <andrew.goodbody@linaro.org>; Sumit Garg
> <sumit.garg@kernel.org>; Marek Vasut <marex@nabladev.com>; Joseph Guo
> <qijian.guo@nxp.com>; tharvey@gateworks.com; Alice Guo
> <alice.guo@nxp.com>
> 主题: Re: [PATCH v1 07/12] arm: imx952: Add watchdog base address
> definitions
>
> Hi Alice,
>
> On Thu, Feb 5, 2026 at 12:16 PM <alice.guo@oss.nxp.com> wrote:
> >
> > From: Alice Guo <alice.guo@nxp.com>
> >
> > Add WDG3, WDG4 and WDG5 base addresses for i.MX952.
> >
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > ---
> > arch/arm/include/asm/arch-imx9/imx-regs.h | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
> b/arch/arm/include/asm/arch-imx9/imx-regs.h
> > index 2d084e5227a..7c7a34f74af 100644
> > --- a/arch/arm/include/asm/arch-imx9/imx-regs.h
> > +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
> > @@ -17,6 +17,11 @@
> >
> > #define ANATOP_BASE_ADDR 0x44480000UL
> >
> > +#ifdef CONFIG_IMX952
> > +#define WDG3_BASE_ADDR 0x420b0000UL
> > +#define WDG4_BASE_ADDR 0x420c0000UL
> > +#define WDG5_BASE_ADDR 0x420d0000UL
> > +#else
> > #ifdef CONFIG_IMX94
> > #define WDG3_BASE_ADDR 0x49220000UL
> > #define WDG4_BASE_ADDR 0x49230000UL
> > @@ -25,6 +30,7 @@
> > #define WDG4_BASE_ADDR 0x424a0000UL
> > #endif
> > #define WDG5_BASE_ADDR 0x424b0000UL
> > +#endif
>
> Can we improve this and retrieve the watchdog base address from the
> devicetree?
Hi Fabio,
Thanks for the suggestion. Using the device tree would be cleaner, but this patch follows the existing i.MX9 imx-regs.h pattern. I suggest we merge this patch to keep consistency with the current codebase. Thoughts?
Best regards,
Alice Guo
^ permalink raw reply [flat|nested] 33+ messages in thread
* 回复: [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux
2026-02-05 15:38 ` Tom Rini
@ 2026-02-09 10:34 ` Alice Guo (OSS)
2026-02-09 14:03 ` Tom Rini
0 siblings, 1 reply; 33+ messages in thread
From: Alice Guo (OSS) @ 2026-02-09 10:34 UTC (permalink / raw)
To: Tom Rini, Alice Guo (OSS)
Cc: dl-uboot-imx, u-boot@lists.denx.de, Stefano Babic, Fabio Estevam,
Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Ross, Fedor, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, tharvey@gateworks.com, Alice Guo
> -----邮件原件-----
> 发件人: Tom Rini <trini@konsulko.com>
> 发送时间: 2026年2月5日 23:39
> 收件人: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> 抄送: dl-uboot-imx <uboot-imx@nxp.com>; u-boot@lists.denx.de; Stefano
> Babic <sbabic@nabladev.com>; Fabio Estevam <festevam@gmail.com>; Peng
> Fan <peng.fan@nxp.com>; Ye Li <ye.li@nxp.com>; Jindong Yue
> <jindong.yue@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Marek Vasut
> <marek.vasut+renesas@mailbox.org>; Rasmus Villemoes <ravi@prevas.dk>;
> Ross, Fedor <fedor.ross@ifm.com>; João Paulo Gonçalves
> <joao.goncalves@toradex.com>; Patrice Chotard
> <patrice.chotard@foss.st.com>; Valentin Caron <valentin.caron@foss.st.com>;
> Vinh Nguyen <vinh.nguyen.xz@renesas.com>; Sam Protsenko
> <semen.protsenko@linaro.org>; Ranjani Vaidyanathan
> <ranjani.vaidyanathan@nxp.com>; Ji Luo <ji.luo@nxp.com>; Frank Li
> <frank.li@nxp.com>; Sumit Garg <sumit.garg@oss.qualcomm.com>; Adam
> Ford <aford173@gmail.com>; Frieder Schrempf
> <frieder.schrempf@kontron.de>; David Zang <davidzangcs@gmail.com>;
> Andrew Goodbody <andrew.goodbody@linaro.org>; Sumit Garg
> <sumit.garg@kernel.org>; Marek Vasut <marex@nabladev.com>; Joseph Guo
> <qijian.guo@nxp.com>; tharvey@gateworks.com; Alice Guo
> <alice.guo@nxp.com>
> 主题: Re: [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952
> device tree from Linux
>
> On Thu, Feb 05, 2026 at 09:55:16PM +0800, alice.guo@oss.nxp.com wrote:
>
> > From: Alice Guo <alice.guo@nxp.com>
> >
> > Sync i.MX952 device tree files from linux-next next-20260202:
> > - Add imx952.dtsi for SoC
> > - Add imx952-evk.dts for i.MX952 EVK board
> > - Add imx952-*.h headers for clock, pinctrl and power
> >
> > Imported from linux-next commit 193579fe0138 ("Add linux-next specific
> > ifiles for 20260202")
> >
> > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > ---
> > dts/upstream/src/arm64/freescale/imx952-clock.h | 215 ++++
> > dts/upstream/src/arm64/freescale/imx952-evk.dts | 596 ++++++++++
> > dts/upstream/src/arm64/freescale/imx952-pinfunc.h | 867
> ++++++++++++++
> > dts/upstream/src/arm64/freescale/imx952-power.h | 44 +
> > dts/upstream/src/arm64/freescale/imx952.dtsi | 1266
> +++++++++++++++++++++
> > 5 files changed, 2988 insertions(+)
>
> This needs to be done (as a series of, if needed) tools/update-subtree.sh
> cherry-pick operations. That gives the right commit message format that
> shows these are changes from upstream.
>
> --
> Tom
Hi Tom,
Thank you for the review. These i.MX952 files are not yet available in the devicetree-rebasing repository, so I cannot use the standard workflow: ./tools/update-subtree.sh pick dts <devicetree-rebasing-commit-id>
Should I wait for the devicetree-rebasing sync?
Best regards,
Alice Guo
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions
2026-02-09 10:24 ` 回复: " Alice Guo (OSS)
@ 2026-02-09 11:21 ` Fabio Estevam
0 siblings, 0 replies; 33+ messages in thread
From: Fabio Estevam @ 2026-02-09 11:21 UTC (permalink / raw)
To: Alice Guo (OSS)
Cc: dl-uboot-imx, u-boot@lists.denx.de, Stefano Babic, Tom Rini,
Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Ross, Fedor, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, tharvey@gateworks.com, Alice Guo
Hi Alice,
On Mon, Feb 9, 2026 at 7:24 AM Alice Guo (OSS) <alice.guo@oss.nxp.com> wrote:
> Hi Fabio,
>
> Thanks for the suggestion. Using the device tree would be cleaner, but this patch follows the existing i.MX9 imx-regs.h pattern. I suggest we merge this patch to keep consistency with the current codebase. Thoughts?
If we always follow the existing codebase, we'll never improve it.
Please try retrieving the watchdog base from the devicetree, so we can
make the code better.
Thanks
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: 回复: [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux
2026-02-09 10:34 ` 回复: " Alice Guo (OSS)
@ 2026-02-09 14:03 ` Tom Rini
0 siblings, 0 replies; 33+ messages in thread
From: Tom Rini @ 2026-02-09 14:03 UTC (permalink / raw)
To: Alice Guo (OSS)
Cc: dl-uboot-imx, u-boot@lists.denx.de, Stefano Babic, Fabio Estevam,
Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Ross, Fedor, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, David Zang, Andrew Goodbody, Sumit Garg,
Marek Vasut, Joseph Guo, tharvey@gateworks.com, Alice Guo
[-- Attachment #1: Type: text/plain, Size: 3088 bytes --]
On Mon, Feb 09, 2026 at 10:34:24AM +0000, Alice Guo (OSS) wrote:
> > -----邮件原件-----
> > 发件人: Tom Rini <trini@konsulko.com>
> > 发送时间: 2026年2月5日 23:39
> > 收件人: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> > 抄送: dl-uboot-imx <uboot-imx@nxp.com>; u-boot@lists.denx.de; Stefano
> > Babic <sbabic@nabladev.com>; Fabio Estevam <festevam@gmail.com>; Peng
> > Fan <peng.fan@nxp.com>; Ye Li <ye.li@nxp.com>; Jindong Yue
> > <jindong.yue@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Marek Vasut
> > <marek.vasut+renesas@mailbox.org>; Rasmus Villemoes <ravi@prevas.dk>;
> > Ross, Fedor <fedor.ross@ifm.com>; João Paulo Gonçalves
> > <joao.goncalves@toradex.com>; Patrice Chotard
> > <patrice.chotard@foss.st.com>; Valentin Caron <valentin.caron@foss.st.com>;
> > Vinh Nguyen <vinh.nguyen.xz@renesas.com>; Sam Protsenko
> > <semen.protsenko@linaro.org>; Ranjani Vaidyanathan
> > <ranjani.vaidyanathan@nxp.com>; Ji Luo <ji.luo@nxp.com>; Frank Li
> > <frank.li@nxp.com>; Sumit Garg <sumit.garg@oss.qualcomm.com>; Adam
> > Ford <aford173@gmail.com>; Frieder Schrempf
> > <frieder.schrempf@kontron.de>; David Zang <davidzangcs@gmail.com>;
> > Andrew Goodbody <andrew.goodbody@linaro.org>; Sumit Garg
> > <sumit.garg@kernel.org>; Marek Vasut <marex@nabladev.com>; Joseph Guo
> > <qijian.guo@nxp.com>; tharvey@gateworks.com; Alice Guo
> > <alice.guo@nxp.com>
> > 主题: Re: [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952
> > device tree from Linux
> >
> > On Thu, Feb 05, 2026 at 09:55:16PM +0800, alice.guo@oss.nxp.com wrote:
> >
> > > From: Alice Guo <alice.guo@nxp.com>
> > >
> > > Sync i.MX952 device tree files from linux-next next-20260202:
> > > - Add imx952.dtsi for SoC
> > > - Add imx952-evk.dts for i.MX952 EVK board
> > > - Add imx952-*.h headers for clock, pinctrl and power
> > >
> > > Imported from linux-next commit 193579fe0138 ("Add linux-next specific
> > > ifiles for 20260202")
> > >
> > > Signed-off-by: Alice Guo <alice.guo@nxp.com>
> > > ---
> > > dts/upstream/src/arm64/freescale/imx952-clock.h | 215 ++++
> > > dts/upstream/src/arm64/freescale/imx952-evk.dts | 596 ++++++++++
> > > dts/upstream/src/arm64/freescale/imx952-pinfunc.h | 867
> > ++++++++++++++
> > > dts/upstream/src/arm64/freescale/imx952-power.h | 44 +
> > > dts/upstream/src/arm64/freescale/imx952.dtsi | 1266
> > +++++++++++++++++++++
> > > 5 files changed, 2988 insertions(+)
> >
> > This needs to be done (as a series of, if needed) tools/update-subtree.sh
> > cherry-pick operations. That gives the right commit message format that
> > shows these are changes from upstream.
> >
> > --
> > Tom
>
> Hi Tom,
>
> Thank you for the review. These i.MX952 files are not yet available in the devicetree-rebasing repository, so I cannot use the standard workflow: ./tools/update-subtree.sh pick dts <devicetree-rebasing-commit-id>
>
> Should I wait for the devicetree-rebasing sync?
Yes, or not use OF_UPSTREAM until the device tree are in an upstream
kernel tag.
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support
2026-02-05 13:55 ` [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support alice.guo
2026-02-06 0:45 ` Peng Fan
@ 2026-02-22 1:34 ` David Zang
1 sibling, 0 replies; 33+ messages in thread
From: David Zang @ 2026-02-22 1:34 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Stefano Babic, Fabio Estevam,
Tom Rini, Peng Fan, Ye Li, Jindong Yue, Jacky Bai, Marek Vasut,
Rasmus Villemoes, Fedor Ross, João Paulo Gonçalves,
Patrice Chotard, Valentin Caron, Vinh Nguyen, Sam Protsenko,
Ranjani Vaidyanathan, Ji Luo, Frank Li, Sumit Garg, Adam Ford,
Frieder Schrempf, Andrew Goodbody, Sumit Garg, Marek Vasut,
Joseph Guo, Tim Harvey, Alice Guo
On Thu, Feb 5, 2026 at 9:16 AM <alice.guo@oss.nxp.com> wrote:
> From: Alice Guo <alice.guo@nxp.com>
>
> Add basic SoC support for i.MX952:
> - Add CONFIG_IMX952 Kconfig option
> - Include i.MX952 clock and power headers
> - Set CPU speed grade to 1.7GHz for i.MX952
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
> ---
> arch/arm/mach-imx/imx9/Kconfig | 9 +++++++++
> arch/arm/mach-imx/imx9/scmi/common.h | 10 ++++++++++
> arch/arm/mach-imx/imx9/scmi/soc.c | 2 ++
> 3 files changed, 21 insertions(+)
>
>
Reviewed-by: David Zang <davidzangcs@gmail.com>
David
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2026-02-22 6:59 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-05 13:55 [PATCH 00/12] imx: add i.MX952 support alice.guo
2026-02-05 13:55 ` [PATCH v1 01/12] imx9: scmi: Get DDR size through SM SCMI API alice.guo
2026-02-06 0:34 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 02/12] imx95/imx94: Remove board_phys_sdram_size from each board alice.guo
2026-02-06 0:35 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 03/12] pinctrl: nxp: Add i.MX952 support alice.guo
2026-02-06 0:36 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 04/12] arm: imx: Add i.MX952 CPU type support alice.guo
2026-02-06 0:37 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 05/12] imx: ele_ahab: Add i.MX952 support to display_life_cycle() alice.guo
2026-02-06 0:38 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 06/12] imx: container: Add i.MX952 support to get_imageset_end() alice.guo
2026-02-06 0:40 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 07/12] arm: imx952: Add watchdog base address definitions alice.guo
2026-02-06 0:41 ` Peng Fan
2026-02-06 3:59 ` Fabio Estevam
2026-02-09 10:24 ` 回复: " Alice Guo (OSS)
2026-02-09 11:21 ` Fabio Estevam
2026-02-05 13:55 ` [PATCH v1 08/12] arm: imx9: Add i.MX952 SoC support alice.guo
2026-02-06 0:45 ` Peng Fan
2026-02-22 1:34 ` David Zang
2026-02-05 13:55 ` [PATCH v1 09/12] cpu: imx952: Add i.MX952 support alice.guo
2026-02-06 0:46 ` Peng Fan
2026-02-05 13:55 ` [PATCH v1 10/12] dts: upstream: arm64: freescale: Sync i.MX952 device tree from Linux alice.guo
2026-02-05 15:38 ` Tom Rini
2026-02-09 10:34 ` 回复: " Alice Guo (OSS)
2026-02-09 14:03 ` Tom Rini
2026-02-05 13:55 ` [PATCH v1 11/12] arm: dts: Add U-Boot device tree for i.MX952 EVK alice.guo
2026-02-06 0:51 ` Peng Fan
2026-02-06 1:27 ` Tom Rini
2026-02-05 13:55 ` [PATCH v1 12/12] board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support alice.guo
2026-02-05 15:45 ` Tom Rini
2026-02-06 1:24 ` Peng Fan
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