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>+ label = "i2c3_io"; >+}; >+ >+&i2c4_pcal6408 { >+ compatible = "ti,tca6408"; >+ label = "i2c4_io"; >+}; >+ >+&pcal6416 { >+ compatible = "ti,tca6416"; >+ label = "i2c6_io"; >+}; >+ >+&pcal6524 { >+ label = "i2c7_io"; >+}; >+ >+&usb1 { >+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; >+ /delete-property/power-domains; >+ bootph-pre-ram; >+ extcon = <&ptn5110>; >+}; >+ >+&usb2 { >+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; >+ /delete-property/power-domains; >+ bootph-pre-ram; >+}; >+ >+&usbmisc1 { >+ bootph-pre-ram; >+}; >+ >+&usbmisc2 { >+ bootph-pre-ram; >+}; >+ >+&usbphynop1 { >+ bootph-pre-ram; >+}; >+ >+&usbphynop2 { >+ bootph-pre-ram; >+}; >+ >+&wdog3 { >+ status = "disabled"; >+}; >diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi >new file mode 100644 >index 00000000000..208931ba884 >--- /dev/null >+++ b/arch/arm/dts/imx952-u-boot.dtsi >@@ -0,0 +1,327 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Copyright 2026 NXP >+ */ >+ >+/ { >+ binman { >+ multiple-images; >+ >+ m33-oei-ddrfw { >+ pad-byte = <0x00>; >+ align-size = <0x8>; >+ filename = "m33-oei-ddrfw.bin"; >+ >+ oei-m33-ddr { >+ align-size = <0x4>; >+ filename = "oei-m33-ddr.bin"; >+ type = "blob-ext"; >+ }; >+ >+ imx-lpddr { >+ type = "nxp-header-ddrfw"; >+ >+ imx-lpddr-imem { >+ filename = "lpddr4x_imem_v202409.bin"; >+ type = "blob-ext"; >+ }; >+ >+ imx-lpddr-dmem { >+ filename = "lpddr4x_dmem_v202409.bin"; >+ type = "blob-ext"; >+ }; >+ }; >+ >+ imx-lpddr-qb { >+ type = "nxp-header-ddrfw"; >+ >+ imx-lpddr-imem-qb { >+ filename = "lpddr4x_imem_qb_v202409.bin"; >+ type = "blob-ext"; >+ }; >+ >+ imx-lpddr-dmem-qb { >+ filename = "lpddr4x_dmem_qb_v202409.bin"; >+ type = "blob-ext"; >+ }; >+ }; >+ }; >+ >+ imx-boot { >+ filename = "flash.bin"; >+ pad-byte = <0x00>; >+ >+ spl { >+ type = "nxp-imx9image"; >+ cfg-path = "spl/u-boot-spl.cfgout"; >+ args; >+ >+ cntr-version = <2>; >+ boot-from = "sd"; >+ soc-type = "IMX9"; >+ append = "mx952a0-ahab-container.img"; >+ container; >+ dummy-ddr; >+ image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; >+ hold = <0x10000>; >+ image1 = "m33", "m33_image.bin", "0x1ffc0000"; >+ image2 = "a55", "spl/u-boot-spl.bin", "0x20480000"; >+ dummy-v2x = <0x8b000000>; >+ }; >+ >+ u-boot { >+ type = "nxp-imx9image"; >+ cfg-path = "u-boot-container.cfgout"; >+ args; >+ >+ cntr-version = <2>; >+ boot-from = "sd"; >+ soc-type = "IMX9"; >+ container; >+ image0 = "a55", "bl31.bin", "0x8a200000"; >+ image1 = "a55", "u-boot.bin", "0x90200000"; >+ }; >+ }; >+ }; >+ >+ chosen { >+ bootargs = "console=ttyLP0,115200 earlycon"; >+ }; >+ >+ aliases { >+ usb_gadget0 = &usbg1; >+ usb_gadget1 = &usbg2; >+ }; >+ >+ usbg1: usbg1 { >+ compatible = "fsl,imx27-usb-gadget"; >+ dr_mode = "peripheral"; >+ chipidea,usb = <&usb1>; >+ bootph-pre-ram; >+ status = "okay"; >+ }; >+ >+ usbg2: usbg2 { >+ compatible = "fsl,imx27-usb-gadget"; >+ dr_mode = "peripheral"; >+ chipidea,usb = <&usb2>; >+ bootph-pre-ram; >+ status = "okay"; >+ }; The above two nodes does not have a working driver in upstream. >+ >+ reg_m2_pwr: regulator-m2-pwr { >+ compatible = "regulator-fixed"; >+ regulator-name = "M.2-power"; >+ regulator-min-microvolt = <3300000>; >+ regulator-max-microvolt = <3300000>; >+ gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; >+ enable-active-high; >+ /* >+ * M.2 device only can be enabled(W_DISABLE1#) after all Power >+ * Rails reach their minimum operating voltage (PCI Express M.2 >+ * Specification r5.1 3.1.4 Power-up Timing). >+ * Set a delay equal to the max value of Tsettle here. >+ */ >+ startup-delay-us = <5000>; >+ }; >+}; >+ >+&A55_0 { >+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; >+ /delete-property/ power-domains; >+}; >+ >+&A55_1 { >+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; >+ /delete-property/ power-domains; >+}; >+ >+&A55_2 { >+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; >+ /delete-property/ power-domains; >+}; >+ >+&A55_3 { >+ clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; >+ /delete-property/ power-domains; >+}; >+ >+&aips1 { >+ bootph-all; >+}; >+ >+&aips2 { >+ bootph-all; >+}; >+ >+&aips3 { >+ bootph-all; >+}; >+ >+&clk_ext1 { >+ bootph-all; >+}; >+ >+&clk_dummy { >+ bootph-all; >+}; >+ >+&clk_osc_24m { >+ bootph-all; >+}; >+ >+&elemu1 { >+ status = "okay"; >+ bootph-all; >+}; >+ >+&elemu3 { >+ status = "okay"; >+ bootph-all; >+}; >+ >+&{/firmware} { >+ bootph-all; >+}; >+ >+&{/firmware/scmi} { >+ bootph-all; >+}; >+ >+&{/firmware/scmi/protocol@11} { >+ bootph-all; >+}; >+ >+&{/firmware/scmi/protocol@13} { >+ bootph-all; >+}; >+ >+&{/firmware/scmi/protocol@14} { >+ bootph-all; >+}; >+ >+&{/firmware/scmi/protocol@15} { >+ bootph-all; >+}; >+ >+&{/firmware/scmi/protocol@19} { >+ bootph-all; >+}; >+ >+&gpio1 { >+ reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; >+}; >+ >+&gpio2 { >+ reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>; >+ bootph-pre-ram; >+ /* >+ * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2 >+ * is assigned to M7, disable gpio2 here >+ */ >+ status = "disabled"; >+}; >+ >+&gpio3 { >+ reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>; >+ bootph-pre-ram; >+}; >+ >+&gpio4 { >+ reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>; >+ bootph-pre-ram; >+}; >+ >+&gpio5 { >+ reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>; >+ bootph-pre-ram; >+}; >+ >+&lpuart1 { >+ bootph-pre-ram; >+}; >+ >+&mu2 { >+ bootph-all; >+}; >+ >+®_usdhc2_vmmc { >+ bootph-pre-ram; >+}; >+ >+&scmi_buf0 { >+ reg = <0x0 0x400>; >+ bootph-all; >+}; >+ >+&scmi_buf1 { >+ bootph-all; >+}; >+ >+&{/soc} { >+ bootph-all; >+}; >+ >+&sram0 { >+ bootph-all; >+}; >+ >+&usdhc1 { >+ bootph-pre-ram; >+}; >+ >+&usdhc2 { >+ bootph-pre-ram; >+}; >+ >+&scmi_iomuxc { >+ pinctrl-names = "default"; >+ pinctrl-0 = <&pinctrl_hog>; >+ >+ pinctrl_hog: hoggrp { >+ bootph-pre-ram; >+ >+ fsl,pins = < >+ IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x3fe >+ IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e >+ IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x3fe >+ IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x3fe >+ >; Add a comment for the settings, why they needs to be set in hog. >+ }; >+}; >+ >+&pinctrl_uart1 { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc1 { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc1_100mhz { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc1_200mhz { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc2 { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc2_100mhz { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc2_200mhz { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_usdhc2_gpio { >+ bootph-pre-ram; >+}; >+ >+&pinctrl_reg_usdhc2_vmmc { >+ bootph-pre-ram; >+}; Regards Peng > >-- >2.43.0 >