From: Leo Liang <ycliang@andestech.com>
To: Uros Stajic <uros.stajic@htecgroup.com>
Cc: "u-boot@lists.denx.de" <u-boot@lists.denx.de>,
Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
Chao-ying Fu <cfu@mips.com>
Subject: Re: [PATCH v5 1/8] riscv: Add initial support for P8700 SoC
Date: Mon, 9 Feb 2026 19:24:16 +0800 [thread overview]
Message-ID: <aYnD4FRyVWrDEflA@swlinux02> (raw)
In-Reply-To: <20251224154449.946780-2-uros.stajic@htecgroup.com>
On Wed, Dec 24, 2025 at 03:45:22PM +0000, Uros Stajic wrote:
> From: Chao-ying Fu <cfu@mips.com>
>
> Add initial platform support for the P8700-F, a high-performance
> multi-core RV64GC SoC with optional multi-cluster configuration and
> hardware multithreading.
>
> This patch introduces the initial platform code necessary to support
> the P8700 CPU in U-Boot.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Uros Stajic <uros.stajic@htecgroup.com>
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/cpu/p8700/Kconfig | 14 +++
> arch/riscv/cpu/p8700/Makefile | 7 ++
> arch/riscv/cpu/p8700/cache.c | 93 ++++++++++++++++++
> arch/riscv/cpu/p8700/cpu.c | 111 ++++++++++++++++++++++
> arch/riscv/cpu/p8700/dram.c | 37 ++++++++
> arch/riscv/include/asm/arch-p8700/p8700.h | 110 +++++++++++++++++++++
> 7 files changed, 373 insertions(+)
> create mode 100644 arch/riscv/cpu/p8700/Kconfig
> create mode 100644 arch/riscv/cpu/p8700/Makefile
> create mode 100644 arch/riscv/cpu/p8700/cache.c
> create mode 100644 arch/riscv/cpu/p8700/cpu.c
> create mode 100644 arch/riscv/cpu/p8700/dram.c
> create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2026-02-09 11:24 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-24 15:44 [PATCH v5 0/8] riscv: Add support for P8700 platform on Boston board Uros Stajic
2025-12-24 15:45 ` [PATCH v5 1/8] riscv: Add initial support for P8700 SoC Uros Stajic
2026-02-09 11:24 ` Leo Liang [this message]
2026-03-17 8:36 ` Leo Liang
2026-03-27 13:46 ` Uros Stajic
2025-12-24 15:45 ` [PATCH v5 2/8] board: boston-riscv: Add initial support for P8700 Boston board Uros Stajic
2026-02-09 11:25 ` Leo Liang
2026-03-17 8:48 ` Leo Liang
2026-03-18 11:16 ` Conor Dooley
2026-03-27 13:48 ` Uros Stajic
2025-12-24 15:46 ` [PATCH v5 3/8] gpio: Add GPIO driver for Intel EG20T Uros Stajic
2025-12-24 15:46 ` [PATCH v5 4/8] pci: xilinx: Avoid writing memory base/limit for root bridge Uros Stajic
2025-12-24 15:46 ` [PATCH v5 5/8] riscv: Add syscon driver for MIPS GIC block Uros Stajic
2025-12-24 15:47 ` [PATCH v5 6/8] net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V Uros Stajic
2026-03-17 8:49 ` Leo Liang
2026-03-27 13:49 ` Uros Stajic
2025-12-24 15:47 ` [PATCH v5 7/8] libfdt: Allow non-64b aligned memreserve entries Uros Stajic
2026-03-17 9:06 ` Leo Liang
2026-03-17 13:47 ` Tom Rini
2026-03-27 13:50 ` Uros Stajic
2025-12-24 15:47 ` [PATCH v5 8/8] riscv: p8700: Add Coherence Manager (CM) and IOCU support Uros Stajic
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