From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Tue, 16 Jul 2019 20:57:41 +0800 Subject: [U-Boot] [PATCH v3 01/57] ram: rk3399: Add ddrtype enc macro In-Reply-To: <20190716115745.12585-2-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> <20190716115745.12585-2-jagan@amarulasolutions.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On 2019/7/16 下午7:56, Jagan Teki wrote: > Add simplified and meaningful macro for ddrtype macro. > > Signed-off-by: Jagan Teki > Signed-off-by: YouMin Chen Reviewed-by: Kever Yang Thanks,  - Kever > --- > arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 + > drivers/ram/rockchip/sdram_rk3399.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h > index b7549f5d8a..92a4c485c2 100644 > --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h > +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h > @@ -72,6 +72,7 @@ struct sdram_base_params { > #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) > #define SYS_REG_ROW_3_4_MASK 1 > #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) > +#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) > #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) > #define SYS_REG_RANK_MASK 1 > #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 9a60c24135..f58836c037 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -1076,7 +1076,7 @@ static void dram_all_config(struct dram_info *dram, > u32 sys_reg = 0; > unsigned int channel, idx; > > - sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; > + sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); > sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT; > > for (channel = 0, idx = 0;