From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7709C433EF for ; Tue, 22 Mar 2022 14:36:48 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C0ABF83AF8; Tue, 22 Mar 2022 15:36:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Rxjwzra0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C9C7383AF9; Tue, 22 Mar 2022 15:36:43 +0100 (CET) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 816AB839C7 for ; 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Tue, 22 Mar 2022 09:36:32 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 22 Mar 2022 09:36:32 -0500 Received: from [128.247.81.242] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 22MEaWna045059; Tue, 22 Mar 2022 09:36:32 -0500 Message-ID: Date: Tue, 22 Mar 2022 09:36:32 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 2/2] ram: k3-ddrss: Fix register definitions Content-Language: en-US To: Dominic Rath , , , References: <606611fc-66b1-5a7f-001a-b2c439beef08@ibv-augsburg.net> From: Dave Gerlach In-Reply-To: <606611fc-66b1-5a7f-001a-b2c439beef08@ibv-augsburg.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi, On 3/22/22 07:11, Dominic Rath wrote: > The K3 DDRSS used by AM64x and J721e (and probably J7200 in the future) > used to define only two register ranges: one labeled "cfg" that was > internally referenced as "DDRSS wrapper", and the LPDDR4 FSP handshake > registers in the CTRL_MMR register space, labeled "ctrl_mmr_lp4". > > The address specified as the "cfg" register space was actually the > DDR controller's configuration registers, not the wrapper. > > The "cfg" registers were mostly used correctly as the address passed > to Cadence code that actually configured the DDR controller and > subsystems, but the code also attempted to use this register space when > it actually wanted to write the DDRSS_V2A_CTL_REG and DDRSS_ECC_CTRL_REG > registers. > > This patch adds a third register property "ddrss", uses that for the > DDRSS wrapper, and continues to use the "cfg" property for the actual > controller configuration registers. > > The "cfg" register space was also configured too small at 16 KB. > The TRMs say the range is 32KB, and the PHY registers actually start > at the 16KB offset. > > Signed-off-by: Dominic Rath > --- I just introduced this same change last week here to add ecc support for am64x: https://lore.kernel.org/u-boot/20220317170346.31162-6-d-gerlach@ti.com/ https://lore.kernel.org/u-boot/20220317170346.31162-8-d-gerlach@ti.com/ Major difference in approach is that I made this an optional region, as J721e does not require it. Regards, Dave > arch/arm/dts/k3-am64-ddr.dtsi | 5 +++-- > arch/arm/dts/k3-j721e-ddr.dtsi | 5 +++-- > drivers/ram/k3-ddrss/k3-ddrss.c | 12 ++++++++++-- > 3 files changed, 16 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi > index 026a547f0e..967bd55e75 100644 > --- a/arch/arm/dts/k3-am64-ddr.dtsi > +++ b/arch/arm/dts/k3-am64-ddr.dtsi > @@ -6,9 +6,10 @@ > / { > memorycontroller: memorycontroller@f300000 { > compatible = "ti,am64-ddrss"; > - reg = <0x00 0x0f308000 0x00 0x4000>, > + reg = <0x00 0x0f300000 0x00 0x200>, > + <0x00 0x0f308000 0x00 0x8000>, > <0x00 0x43014000 0x00 0x100>; > - reg-names = "cfg", "ctrl_mmr_lp4"; > + reg-names = "ddrss", "cfg", "ctrl_mmr_lp4"; > power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>, > <&k3_pds 55 TI_SCI_PD_SHARED>; > clocks = <&k3_clks 138 0>, <&k3_clks 16 4>; > diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi > index 21d63802a5..8f1b792849 100644 > --- a/arch/arm/dts/k3-j721e-ddr.dtsi > +++ b/arch/arm/dts/k3-j721e-ddr.dtsi > @@ -6,9 +6,10 @@ > / { > memorycontroller: memorycontroller@0298e000 { > compatible = "ti,j721e-ddrss"; > - reg = <0x0 0x02990000 0x0 0x4000>, > + reg = <0x0 0x02980000 0x0 0x200>, > + <0x0 0x02990000 0x0 0x8000>, > <0x0 0x0114000 0x0 0x100>; > - reg-names = "cfg", "ctrl_mmr_lp4"; > + reg-names = "ddrss", "cfg", "ctrl_mmr_lp4"; > power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>, > <&k3_pds 90 TI_SCI_PD_SHARED>; > clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; > diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c > b/drivers/ram/k3-ddrss/k3-ddrss.c > index 261ba64506..7e2a4c5811 100644 > --- a/drivers/ram/k3-ddrss/k3-ddrss.c > +++ b/drivers/ram/k3-ddrss/k3-ddrss.c > @@ -105,6 +105,7 @@ struct k3_msmc { > struct k3_ddrss_desc { > struct udevice *dev; > void __iomem *ddrss_ss_cfg; > + void __iomem *ddrss_ctrl_cfg; > void __iomem *ddrss_ctrl_mmr; > struct power_domain ddrcfg_pwrdmn; > struct power_domain ddrdata_pwrdmn; > @@ -314,13 +315,20 @@ static int k3_ddrss_ofdata_to_priv(struct udevice > *dev) > debug("%s(dev=%p)\n", __func__, dev); > - reg = dev_read_addr_name(dev, "cfg"); > + reg = dev_read_addr_name(dev, "ddrss"); > if (reg == FDT_ADDR_T_NONE) { > dev_err(dev, "No reg property for DDRSS wrapper logic\n"); > return -EINVAL; > } > ddrss->ddrss_ss_cfg = (void *)reg; > + reg = dev_read_addr_name(dev, "cfg"); > + if (reg == FDT_ADDR_T_NONE) { > + dev_err(dev, "No reg property for controller registers\n"); > + return -EINVAL; > + } > + ddrss->ddrss_ctrl_cfg = (void *)reg; > + > reg = dev_read_addr_name(dev, "ctrl_mmr_lp4"); > if (reg == FDT_ADDR_T_NONE) { > dev_err(dev, "No reg property for CTRL MMR\n"); > @@ -403,7 +411,7 @@ void k3_lpddr4_init(struct k3_ddrss_desc *ddrss) > hang(); > } > - config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg; > + config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctrl_cfg; > config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler; > status = driverdt->init(pd, config);