* [PATCH 1/7] drivers: pinctrl: Add Qualcomm Milos TLMM driver
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:39 ` Sumit Garg
2026-03-11 14:20 ` [PATCH 2/7] clk/qcom: Add Milos clock driver Luca Weiss
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on Milos SoC, with support for special pins.
Correct pin configuration is required for working debug UART and eMMC/SD
cards.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/pinctrl/qcom/Kconfig | 8 +++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-milos.c | 104 +++++++++++++++++++++++++++++++++++
3 files changed, 113 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 580308621b1..11e6763b5f3 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -54,6 +54,14 @@ config PINCTRL_QCOM_IPQ9574
Say Y here to enable support for pinctrl on the IPQ9574 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_MILOS
+ bool "Qualcomm Milos Pinctrl"
+ default y if PINCTRL_QCOM_GENERIC
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon Milos SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_QCM2290
bool "Qualcomm QCM2290 Pinctrl"
default y if PINCTRL_QCOM_GENERIC
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index b5a111605ed..4096c1aa491 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_QCOM_IPQ5424) += pinctrl-ipq5424.o
obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
+obj-$(CONFIG_PINCTRL_QCOM_MILOS) += pinctrl-milos.o
obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o
diff --git a/drivers/pinctrl/qcom/pinctrl-milos.c b/drivers/pinctrl/qcom/pinctrl-milos.c
new file mode 100644
index 00000000000..974c1a7d594
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-milos.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Milos pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ * (C) Copyright 2025 Luca Weiss <luca.weiss@fairphone.com>
+ *
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup0_se5", 1},
+ {"sdc2_clk", 1},
+ {"sdc2_cmd", 1},
+ {"sdc2_data", 1},
+ {"gpio", 0},
+};
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+#define UFS_RESET(pg_name, ctl, io) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = io, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ }
+
+static const struct msm_special_pin_data msm_special_pins_data[] = {
+ [0] = UFS_RESET("ufs_reset", 0xb4004, 0xb5000),
+ [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xab000, 0, 6),
+ [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xab000, 12, 3),
+ [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xab000, 9, 0),
+};
+
+static const char *milos_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *milos_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector >= 167 && selector <= 170)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
+ msm_special_pins_data[selector - 167].name);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static int milos_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data milos_data = {
+ .pin_data = {
+ .pin_count = 171,
+ .special_pins_start = 167,
+ .special_pins_data = msm_special_pins_data,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = milos_get_function_name,
+ .get_function_mux = milos_get_function_mux,
+ .get_pin_name = milos_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,milos-tlmm", .data = (ulong)&milos_data },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_milos) = {
+ .name = "pinctrl_milos",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
+
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 1/7] drivers: pinctrl: Add Qualcomm Milos TLMM driver
2026-03-11 14:20 ` [PATCH 1/7] drivers: pinctrl: Add Qualcomm Milos TLMM driver Luca Weiss
@ 2026-03-12 7:39 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:39 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:41PM +0100, Luca Weiss wrote:
> Add support for TLMM pin controller block (Top Level Mode Multiplexer)
> on Milos SoC, with support for special pins.
>
> Correct pin configuration is required for working debug UART and eMMC/SD
> cards.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/pinctrl/qcom/Kconfig | 8 +++
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-milos.c | 104 +++++++++++++++++++++++++++++++++++
> 3 files changed, 113 insertions(+)
>
Looks good to me apart from minor comment below, FWIW:
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 580308621b1..11e6763b5f3 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -54,6 +54,14 @@ config PINCTRL_QCOM_IPQ9574
> Say Y here to enable support for pinctrl on the IPQ9574 SoC,
> as well as the associated GPIO driver.
>
> +config PINCTRL_QCOM_MILOS
> + bool "Qualcomm Milos Pinctrl"
> + default y if PINCTRL_QCOM_GENERIC
> + select PINCTRL_QCOM
> + help
> + Say Y here to enable support for pinctrl on the Snapdragon Milos SoC,
> + as well as the associated GPIO driver.
> +
> config PINCTRL_QCOM_QCM2290
> bool "Qualcomm QCM2290 Pinctrl"
> default y if PINCTRL_QCOM_GENERIC
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index b5a111605ed..4096c1aa491 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_QCOM_IPQ5424) += pinctrl-ipq5424.o
> obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
> obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
> +obj-$(CONFIG_PINCTRL_QCOM_MILOS) += pinctrl-milos.o
> obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-milos.c b/drivers/pinctrl/qcom/pinctrl-milos.c
> new file mode 100644
> index 00000000000..974c1a7d594
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-milos.c
> @@ -0,0 +1,104 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm Milos pinctrl
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + * (C) Copyright 2025 Luca Weiss <luca.weiss@fairphone.com>
It's 2026 now, maybe you want to update copyright here?
-Sumit
> + *
> + */
> +
> +#include <dm.h>
> +
> +#include "pinctrl-qcom.h"
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"qup0_se5", 1},
> + {"sdc2_clk", 1},
> + {"sdc2_cmd", 1},
> + {"sdc2_data", 1},
> + {"gpio", 0},
> +};
> +
> +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
> + { \
> + .name = pg_name, \
> + .ctl_reg = ctl, \
> + .io_reg = 0, \
> + .pull_bit = pull, \
> + .drv_bit = drv, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = -1, \
> + }
> +
> +#define UFS_RESET(pg_name, ctl, io) \
> + { \
> + .name = pg_name, \
> + .ctl_reg = ctl, \
> + .io_reg = io, \
> + .pull_bit = 3, \
> + .drv_bit = 0, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = 0, \
> + }
> +
> +static const struct msm_special_pin_data msm_special_pins_data[] = {
> + [0] = UFS_RESET("ufs_reset", 0xb4004, 0xb5000),
> + [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xab000, 0, 6),
> + [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xab000, 12, 3),
> + [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xab000, 9, 0),
> +};
> +
> +static const char *milos_get_function_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *milos_get_pin_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + if (selector >= 167 && selector <= 170)
> + snprintf(pin_name, MAX_PIN_NAME_LEN,
> + msm_special_pins_data[selector - 167].name);
> + else
> + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +
> + return pin_name;
> +}
> +
> +static int milos_get_function_mux(__maybe_unused unsigned int pin,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].val;
> +}
> +
> +static struct msm_pinctrl_data milos_data = {
> + .pin_data = {
> + .pin_count = 171,
> + .special_pins_start = 167,
> + .special_pins_data = msm_special_pins_data,
> + },
> + .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> + .get_function_name = milos_get_function_name,
> + .get_function_mux = milos_get_function_mux,
> + .get_pin_name = milos_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> + { .compatible = "qcom,milos-tlmm", .data = (ulong)&milos_data },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_milos) = {
> + .name = "pinctrl_milos",
> + .id = UCLASS_NOP,
> + .of_match = msm_pinctrl_ids,
> + .ops = &msm_pinctrl_ops,
> + .bind = msm_pinctrl_bind,
> +};
> +
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/7] clk/qcom: Add Milos clock driver
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
2026-03-11 14:20 ` [PATCH 1/7] drivers: pinctrl: Add Qualcomm Milos TLMM driver Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:45 ` Sumit Garg
2026-03-11 14:20 ` [PATCH 3/7] phy: qcom: Add Milos to QMP UFS PHY driver Luca Weiss
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
Add Clock driver for the GCC block found in the Milos SoC.
The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref"
clock), so we need to pass that as well.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-milos.c | 224 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 233 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8504ed5d656..0a2ce55aaa2 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -47,6 +47,14 @@ config CLK_QCOM_IPQ9574
on the Snapdragon IPQ9574 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_MILOS
+ bool "Qualcomm Milos GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon Milos SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
config CLK_QCOM_QCM2290
bool "Qualcomm QCM2290 GCC"
select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 82a5b166196..b96d61b603e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o
obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
+obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o
obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
diff --git a/drivers/clk/qcom/clock-milos.c b/drivers/clk/qcom/clock-milos.c
new file mode 100644
index 00000000000..04f46b943c1
--- /dev/null
+++ b/drivers/clk/qcom/clock-milos.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm Milos
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ * (C) Copyright 2025 Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,milos-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+#include "clock-qcom.h"
+
+/* On-board TCXO, TOFIX get from DT */
+#define TCXO_RATE 76800000
+
+/* bi_tcxo_div4 divided after RPMh output */
+#define TCXO_DIV4_RATE (TCXO_RATE / 4)
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s3_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(51200000, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
+ F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
+ F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static ulong milos_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP0_S5_CLK: /* UART5 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s3_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x18500,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x14018,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x3902c,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ clk_rcg_set_rate(priv->base, 0x39044, 0, 0);
+ return TCXO_DIV4_RATE;
+ default:
+ return 0;
+ }
+}
+
+static const struct gate_clk milos_clks[] = {
+ GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x39090, BIT(0)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(27)),
+ GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x52008, BIT(20)),
+ GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x52008, BIT(21)),
+ GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14010, BIT(0)),
+ GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)),
+ GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)),
+};
+
+static int milos_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case GCC_AGGRE_USB3_PRIM_AXI_CLK:
+ qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
+ break;
+ }
+
+ return qcom_gate_clk_en(priv, clk->id);
+}
+
+static const struct qcom_reset_map milos_gcc_resets[] = {
+ [GCC_CAMERA_BCR] = { 0x26000 },
+ [GCC_DISPLAY_BCR] = { 0x27000 },
+ [GCC_GPU_BCR] = { 0x71000 },
+ [GCC_PCIE_0_BCR] = { 0x6b000 },
+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+ [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
+ [GCC_PCIE_1_BCR] = { 0x90000 },
+ [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
+ [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
+ [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
+ [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
+ [GCC_PCIE_RSCC_BCR] = { 0x11000 },
+ [GCC_PDM_BCR] = { 0x33000 },
+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x18000 },
+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x1e000 },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_SDCC1_BCR] = { 0xa3000 },
+ [GCC_SDCC2_BCR] = { 0x14000 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB30_PRIM_BCR] = { 0x39000 },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
+ [GCC_VIDEO_BCR] = { 0x32000 },
+};
+
+static const struct qcom_power_map milos_gdscs[] = {
+ [PCIE_0_GDSC] = { 0x6b004 },
+ [PCIE_0_PHY_GDSC] = { 0x6c000 },
+ [PCIE_1_GDSC] = { 0x90004 },
+ [PCIE_1_PHY_GDSC] = { 0xa2000 },
+ [UFS_PHY_GDSC] = { 0x77004 },
+ [UFS_MEM_PHY_GDSC] = { 0x9e000 },
+ [USB30_PRIM_GDSC] = { 0x39004 },
+ [USB3_PHY_GDSC] = { 0x5000c },
+};
+
+static struct msm_clk_data milos_gcc_data = {
+ .resets = milos_gcc_resets,
+ .num_resets = ARRAY_SIZE(milos_gcc_resets),
+ .clks = milos_clks,
+ .num_clks = ARRAY_SIZE(milos_clks),
+ .power_domains = milos_gdscs,
+ .num_power_domains = ARRAY_SIZE(milos_gdscs),
+
+ .enable = milos_enable,
+ .set_rate = milos_set_rate,
+};
+
+static const struct udevice_id gcc_milos_of_match[] = {
+ {
+ .compatible = "qcom,milos-gcc",
+ .data = (ulong)&milos_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_milos) = {
+ .name = "gcc_milos",
+ .id = UCLASS_NOP,
+ .of_match = gcc_milos_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
+static ulong milos_rpmh_clk_set_rate(struct clk *clk, ulong rate)
+{
+ return (clk->rate = rate);
+}
+
+static ulong milos_rpmh_clk_get_rate(struct clk *clk)
+{
+ switch (clk->id) {
+ case RPMH_CXO_CLK:
+ return TCXO_DIV4_RATE;
+ default:
+ return clk->rate;
+ }
+}
+
+static int milos_rpmh_clk_nop(struct clk *clk)
+{
+ return 0;
+}
+
+static struct clk_ops milos_rpmh_clk_ops = {
+ .set_rate = milos_rpmh_clk_set_rate,
+ .get_rate = milos_rpmh_clk_get_rate,
+ .enable = milos_rpmh_clk_nop,
+ .disable = milos_rpmh_clk_nop,
+};
+
+static const struct udevice_id milos_rpmh_clk_ids[] = {
+ { .compatible = "qcom,milos-rpmh-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(milos_rpmh_clk) = {
+ .name = "milos_rpmh_clk",
+ .id = UCLASS_CLK,
+ .of_match = milos_rpmh_clk_ids,
+ .ops = &milos_rpmh_clk_ops,
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/7] clk/qcom: Add Milos clock driver
2026-03-11 14:20 ` [PATCH 2/7] clk/qcom: Add Milos clock driver Luca Weiss
@ 2026-03-12 7:45 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:45 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:42PM +0100, Luca Weiss wrote:
> Add Clock driver for the GCC block found in the Milos SoC.
>
> The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref"
> clock), so we need to pass that as well.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/clk/qcom/Kconfig | 8 ++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-milos.c | 224 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 233 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 8504ed5d656..0a2ce55aaa2 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -47,6 +47,14 @@ config CLK_QCOM_IPQ9574
> on the Snapdragon IPQ9574 SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_MILOS
> + bool "Qualcomm Milos GCC"
> + select CLK_QCOM
> + help
> + Say Y here to enable support for the Global Clock Controller
> + on the Snapdragon Milos SoC. This driver supports the clocks
> + and resets exposed by the GCC hardware block.
> +
> config CLK_QCOM_QCM2290
> bool "Qualcomm QCM2290 GCC"
> select CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 82a5b166196..b96d61b603e 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o
> obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
> +obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o
> obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
> diff --git a/drivers/clk/qcom/clock-milos.c b/drivers/clk/qcom/clock-milos.c
> new file mode 100644
> index 00000000000..04f46b943c1
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-milos.c
> @@ -0,0 +1,224 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm Milos
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + * (C) Copyright 2025 Luca Weiss <luca.weiss@fairphone.com>
Ditto for copyright update.
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <linux/delay.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <linux/bug.h>
> +#include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,milos-gcc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +
> +#include "clock-qcom.h"
> +
> +/* On-board TCXO, TOFIX get from DT */
> +#define TCXO_RATE 76800000
> +
> +/* bi_tcxo_div4 divided after RPMh output */
> +#define TCXO_DIV4_RATE (TCXO_RATE / 4)
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s3_clk_src[] = {
> + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> + F(51200000, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375),
> + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
> + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
> + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> + /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
> + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
> + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
> + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static ulong milos_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> +
> + switch (clk->id) {
> + case GCC_QUPV3_WRAP0_S5_CLK: /* UART5 */
> + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s3_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x18500,
> + freq->pre_div, freq->m, freq->n, freq->src, 16);
> + return freq->freq;
> + case GCC_SDCC2_APPS_CLK:
> + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x14018,
> + freq->pre_div, freq->m, freq->n, freq->src, 8);
> + return freq->freq;
> + case GCC_USB30_PRIM_MASTER_CLK:
> + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, 0x3902c,
> + freq->pre_div, freq->m, freq->n, freq->src, 8);
> + return freq->freq;
> + case GCC_USB30_PRIM_MOCK_UTMI_CLK:
> + clk_rcg_set_rate(priv->base, 0x39044, 0, 0);
> + return TCXO_DIV4_RATE;
> + default:
> + return 0;
> + }
> +}
> +
> +static const struct gate_clk milos_clks[] = {
> + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x39090, BIT(0)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(27)),
> + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x52008, BIT(20)),
> + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x52008, BIT(21)),
> + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14010, BIT(0)),
> + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
> + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)),
> + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)),
> + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)),
> + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)),
> +};
> +
> +static int milos_enable(struct clk *clk)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case GCC_AGGRE_USB3_PRIM_AXI_CLK:
> + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
> + break;
> + }
> +
> + return qcom_gate_clk_en(priv, clk->id);
> +}
> +
> +static const struct qcom_reset_map milos_gcc_resets[] = {
> + [GCC_CAMERA_BCR] = { 0x26000 },
> + [GCC_DISPLAY_BCR] = { 0x27000 },
> + [GCC_GPU_BCR] = { 0x71000 },
> + [GCC_PCIE_0_BCR] = { 0x6b000 },
> + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
> + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
> + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
> + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
> + [GCC_PCIE_1_BCR] = { 0x90000 },
> + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
> + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
> + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
> + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
> + [GCC_PCIE_RSCC_BCR] = { 0x11000 },
> + [GCC_PDM_BCR] = { 0x33000 },
> + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x18000 },
> + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x1e000 },
> + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
> + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
> + [GCC_SDCC1_BCR] = { 0xa3000 },
> + [GCC_SDCC2_BCR] = { 0x14000 },
> + [GCC_UFS_PHY_BCR] = { 0x77000 },
> + [GCC_USB30_PRIM_BCR] = { 0x39000 },
> + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
> + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
> + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
> + [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
> + [GCC_VIDEO_BCR] = { 0x32000 },
> +};
Similar to clocks, we should limit resets to supported peripherals only.
Although I would love to see PCIe and other peripherals support but that
should be functionally complete.
> +
> +static const struct qcom_power_map milos_gdscs[] = {
> + [PCIE_0_GDSC] = { 0x6b004 },
> + [PCIE_0_PHY_GDSC] = { 0x6c000 },
> + [PCIE_1_GDSC] = { 0x90004 },
> + [PCIE_1_PHY_GDSC] = { 0xa2000 },
> + [UFS_PHY_GDSC] = { 0x77004 },
> + [UFS_MEM_PHY_GDSC] = { 0x9e000 },
> + [USB30_PRIM_GDSC] = { 0x39004 },
> + [USB3_PHY_GDSC] = { 0x5000c },
> +};
Ditto here.
-Sumit
> +
> +static struct msm_clk_data milos_gcc_data = {
> + .resets = milos_gcc_resets,
> + .num_resets = ARRAY_SIZE(milos_gcc_resets),
> + .clks = milos_clks,
> + .num_clks = ARRAY_SIZE(milos_clks),
> + .power_domains = milos_gdscs,
> + .num_power_domains = ARRAY_SIZE(milos_gdscs),
> +
> + .enable = milos_enable,
> + .set_rate = milos_set_rate,
> +};
> +
> +static const struct udevice_id gcc_milos_of_match[] = {
> + {
> + .compatible = "qcom,milos-gcc",
> + .data = (ulong)&milos_gcc_data,
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(gcc_milos) = {
> + .name = "gcc_milos",
> + .id = UCLASS_NOP,
> + .of_match = gcc_milos_of_match,
> + .bind = qcom_cc_bind,
> + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
> +
> +static ulong milos_rpmh_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + return (clk->rate = rate);
> +}
> +
> +static ulong milos_rpmh_clk_get_rate(struct clk *clk)
> +{
> + switch (clk->id) {
> + case RPMH_CXO_CLK:
> + return TCXO_DIV4_RATE;
> + default:
> + return clk->rate;
> + }
> +}
> +
> +static int milos_rpmh_clk_nop(struct clk *clk)
> +{
> + return 0;
> +}
> +
> +static struct clk_ops milos_rpmh_clk_ops = {
> + .set_rate = milos_rpmh_clk_set_rate,
> + .get_rate = milos_rpmh_clk_get_rate,
> + .enable = milos_rpmh_clk_nop,
> + .disable = milos_rpmh_clk_nop,
> +};
> +
> +static const struct udevice_id milos_rpmh_clk_ids[] = {
> + { .compatible = "qcom,milos-rpmh-clk" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(milos_rpmh_clk) = {
> + .name = "milos_rpmh_clk",
> + .id = UCLASS_CLK,
> + .of_match = milos_rpmh_clk_ids,
> + .ops = &milos_rpmh_clk_ops,
> + .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/7] phy: qcom: Add Milos to QMP UFS PHY driver
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
2026-03-11 14:20 ` [PATCH 1/7] drivers: pinctrl: Add Qualcomm Milos TLMM driver Luca Weiss
2026-03-11 14:20 ` [PATCH 2/7] clk/qcom: Add Milos clock driver Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:47 ` Sumit Garg
2026-03-11 14:20 ` [PATCH 4/7] regulator: qcom-rpmh-regulator: add support for PM7550 regulators Luca Weiss
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
Import the configuration for the Milos SoC from Linux.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/phy/qcom/phy-qcom-qmp-ufs.c | 88 +++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
index 907f34744eb..80eba734a63 100644
--- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
@@ -119,6 +119,68 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
};
+static const struct qmp_ufs_init_tbl milos_ufsphy_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
+};
+
+static const struct qmp_ufs_init_tbl milos_ufsphy_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc),
+};
+
+static const struct qmp_ufs_init_tbl milos_ufsphy_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
+};
+
+static const struct qmp_ufs_init_tbl milos_ufsphy_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
+};
+
static const struct qmp_ufs_init_tbl sdm845_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
@@ -982,6 +1044,31 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
.rx2 = 0x1a00,
};
+static const struct qmp_ufs_cfg milos_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets_v6,
+
+ .tbls = {
+ .serdes = milos_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(milos_ufsphy_serdes),
+ .tx = milos_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(milos_ufsphy_tx),
+ .rx = milos_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(milos_ufsphy_rx),
+ .pcs = milos_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(milos_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sm8550_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
+ },
+
+ .vreg_list = qmp_ufs_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
+ .regs = ufsphy_v6_regs_layout,
+};
+
static const struct qmp_ufs_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
@@ -1651,6 +1738,7 @@ static struct phy_ops qmp_ufs_ops = {
};
static const struct udevice_id qmp_ufs_ids[] = {
+ { .compatible = "qcom,milos-qmp-ufs-phy", .data = (ulong)&milos_ufsphy_cfg, },
{ .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, },
{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
{ .compatible = "qcom,sm6350-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 3/7] phy: qcom: Add Milos to QMP UFS PHY driver
2026-03-11 14:20 ` [PATCH 3/7] phy: qcom: Add Milos to QMP UFS PHY driver Luca Weiss
@ 2026-03-12 7:47 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:47 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:43PM +0100, Luca Weiss wrote:
> Import the configuration for the Milos SoC from Linux.
Please update commit message to reflect the Linux commit/tag from where
the configuration is imported. With that feel free to add:
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/phy/qcom/phy-qcom-qmp-ufs.c | 88 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> index 907f34744eb..80eba734a63 100644
> --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> @@ -119,6 +119,68 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
> };
>
> +static const struct qmp_ufs_init_tbl milos_ufsphy_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
> +};
> +
> +static const struct qmp_ufs_init_tbl milos_ufsphy_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc),
> +};
> +
> +static const struct qmp_ufs_init_tbl milos_ufsphy_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
> +};
> +
> +static const struct qmp_ufs_init_tbl milos_ufsphy_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> static const struct qmp_ufs_init_tbl sdm845_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
> @@ -982,6 +1044,31 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
> .rx2 = 0x1a00,
> };
>
> +static const struct qmp_ufs_cfg milos_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_ufs_offsets_v6,
> +
> + .tbls = {
> + .serdes = milos_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(milos_ufsphy_serdes),
> + .tx = milos_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(milos_ufsphy_tx),
> + .rx = milos_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(milos_ufsphy_rx),
> + .pcs = milos_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(milos_ufsphy_pcs),
> + },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> +
> + .vreg_list = qmp_ufs_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
> + .regs = ufsphy_v6_regs_layout,
> +};
> +
> static const struct qmp_ufs_cfg sdm845_ufsphy_cfg = {
> .lanes = 2,
>
> @@ -1651,6 +1738,7 @@ static struct phy_ops qmp_ufs_ops = {
> };
>
> static const struct udevice_id qmp_ufs_ids[] = {
> + { .compatible = "qcom,milos-qmp-ufs-phy", .data = (ulong)&milos_ufsphy_cfg, },
> { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, },
> { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
> { .compatible = "qcom,sm6350-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/7] regulator: qcom-rpmh-regulator: add support for PM7550 regulators
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
` (2 preceding siblings ...)
2026-03-11 14:20 ` [PATCH 3/7] phy: qcom: Add Milos to QMP UFS PHY driver Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:48 ` Sumit Garg
2026-03-11 14:20 ` [PATCH 5/7] gpio: qcom: Support GPIOs on PM7550 PMIC Luca Weiss
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
Add the PM7550 regulator data found on Qualcomm Milos devices.
The tables are imported from the Linux driver. The SMPS regulators were
not added now.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/power/regulator/qcom-rpmh-regulator.c | 33 +++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c
index 3f0f1845469..4d65aae1690 100644
--- a/drivers/power/regulator/qcom-rpmh-regulator.c
+++ b/drivers/power/regulator/qcom-rpmh-regulator.c
@@ -640,6 +640,35 @@ static const struct rpmh_vreg_init_data pm6150l_vreg_data[] = {
{}
};
+static const struct rpmh_vreg_init_data pm7550_vreg_data[] = {
+ /* smps1 - smps6 are not added to u-boot yet */
+ RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l2-l3"),
+ RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l4-l5"),
+ RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo515, "vdd-l4-l5"),
+ RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo515, "vdd-l6"),
+ RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l7"),
+ RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo515, "vdd-l8"),
+ RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo515, "vdd-l9-l10"),
+ RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l9-l10"),
+ RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
+ RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo515_mv, "vdd-l12-l14"),
+ RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo515_mv, "vdd-l13-l16"),
+ RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l12-l14"),
+ RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16"),
+ RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo20", "ldo%s20", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo21", "ldo%s21", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo22", "ldo%s22", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo23", "ldo%s23", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
+ {}
+};
+
static const struct rpmh_vreg_init_data pm8150_vreg_data[] = {
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
@@ -946,6 +975,10 @@ static const struct udevice_id rpmh_regulator_ids[] = {
.compatible = "qcom,pm7325-rpmh-regulators",
.data = (ulong)pm7325_vreg_data,
},
+ {
+ .compatible = "qcom,pm7550-rpmh-regulators",
+ .data = (ulong)pm7550_vreg_data,
+ },
{
.compatible = "qcom,pm8150-rpmh-regulators",
.data = (ulong)pm8150_vreg_data,
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 4/7] regulator: qcom-rpmh-regulator: add support for PM7550 regulators
2026-03-11 14:20 ` [PATCH 4/7] regulator: qcom-rpmh-regulator: add support for PM7550 regulators Luca Weiss
@ 2026-03-12 7:48 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:48 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:44PM +0100, Luca Weiss wrote:
> Add the PM7550 regulator data found on Qualcomm Milos devices.
> The tables are imported from the Linux driver. The SMPS regulators were
> not added now.
Extend commit message with Linux tag/commit for the imported tables,
with that:
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/power/regulator/qcom-rpmh-regulator.c | 33 +++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c
> index 3f0f1845469..4d65aae1690 100644
> --- a/drivers/power/regulator/qcom-rpmh-regulator.c
> +++ b/drivers/power/regulator/qcom-rpmh-regulator.c
> @@ -640,6 +640,35 @@ static const struct rpmh_vreg_init_data pm6150l_vreg_data[] = {
> {}
> };
>
> +static const struct rpmh_vreg_init_data pm7550_vreg_data[] = {
> + /* smps1 - smps6 are not added to u-boot yet */
> + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
> + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-l3"),
> + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l2-l3"),
> + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l4-l5"),
> + RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo515, "vdd-l4-l5"),
> + RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo515, "vdd-l6"),
> + RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l7"),
> + RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo515, "vdd-l8"),
> + RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo515, "vdd-l9-l10"),
> + RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l9-l10"),
> + RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
> + RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo515_mv, "vdd-l12-l14"),
> + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo515_mv, "vdd-l13-l16"),
> + RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l12-l14"),
> + RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16"),
> + RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo20", "ldo%s20", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo21", "ldo%s21", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo22", "ldo%s22", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("ldo23", "ldo%s23", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
> + RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
> + {}
> +};
> +
> static const struct rpmh_vreg_init_data pm8150_vreg_data[] = {
> RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
> RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
> @@ -946,6 +975,10 @@ static const struct udevice_id rpmh_regulator_ids[] = {
> .compatible = "qcom,pm7325-rpmh-regulators",
> .data = (ulong)pm7325_vreg_data,
> },
> + {
> + .compatible = "qcom,pm7550-rpmh-regulators",
> + .data = (ulong)pm7550_vreg_data,
> + },
> {
> .compatible = "qcom,pm8150-rpmh-regulators",
> .data = (ulong)pm8150_vreg_data,
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/7] gpio: qcom: Support GPIOs on PM7550 PMIC
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
` (3 preceding siblings ...)
2026-03-11 14:20 ` [PATCH 4/7] regulator: qcom-rpmh-regulator: add support for PM7550 regulators Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:49 ` Sumit Garg
2026-03-11 14:20 ` [PATCH 6/7] qcom_defconfig: Enable Milos clock driver Luca Weiss
2026-03-11 14:20 ` [PATCH 7/7] board/qualcomm: add debug config fragment for Milos Luca Weiss
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
The GPIOs on PM7550 work fine using the qcom_spmi_gpio driver and
enables the use of the Volume Up button on the Fairphone (Gen. 6)
smartphone.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/gpio/qcom_spmi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c
index 1a7c7c48dfc..77a69140213 100644
--- a/drivers/gpio/qcom_spmi_gpio.c
+++ b/drivers/gpio/qcom_spmi_gpio.c
@@ -747,6 +747,7 @@ static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = {
{ .compatible = "qcom,pm6350-gpio" },
{ .compatible = "qcom,pm660l-gpio" },
{ .compatible = "qcom,pm7325-gpio" },
+ { .compatible = "qcom,pm7550-gpio" },
{ .compatible = "qcom,pm8550-gpio" },
{ .compatible = "qcom,pm8550b-gpio" },
{ .compatible = "qcom,pm8550ve-gpio" },
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 5/7] gpio: qcom: Support GPIOs on PM7550 PMIC
2026-03-11 14:20 ` [PATCH 5/7] gpio: qcom: Support GPIOs on PM7550 PMIC Luca Weiss
@ 2026-03-12 7:49 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:49 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:45PM +0100, Luca Weiss wrote:
> The GPIOs on PM7550 work fine using the qcom_spmi_gpio driver and
> enables the use of the Volume Up button on the Fairphone (Gen. 6)
> smartphone.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/gpio/qcom_spmi_gpio.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c
> index 1a7c7c48dfc..77a69140213 100644
> --- a/drivers/gpio/qcom_spmi_gpio.c
> +++ b/drivers/gpio/qcom_spmi_gpio.c
> @@ -747,6 +747,7 @@ static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = {
> { .compatible = "qcom,pm6350-gpio" },
> { .compatible = "qcom,pm660l-gpio" },
> { .compatible = "qcom,pm7325-gpio" },
> + { .compatible = "qcom,pm7550-gpio" },
> { .compatible = "qcom,pm8550-gpio" },
> { .compatible = "qcom,pm8550b-gpio" },
> { .compatible = "qcom,pm8550ve-gpio" },
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 6/7] qcom_defconfig: Enable Milos clock driver
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
` (4 preceding siblings ...)
2026-03-11 14:20 ` [PATCH 5/7] gpio: qcom: Support GPIOs on PM7550 PMIC Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:50 ` Sumit Garg
2026-03-11 14:20 ` [PATCH 7/7] board/qualcomm: add debug config fragment for Milos Luca Weiss
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
Enable the driver so that Milos devices can boot with qcom_defconfig.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index fe5880de1fd..44c1cef725c 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -56,6 +56,7 @@ CONFIG_CLK=y
CONFIG_CLK_STUB=y
CONFIG_CLK_QCOM_APQ8016=y
CONFIG_CLK_QCOM_APQ8096=y
+CONFIG_CLK_QCOM_MILOS=y
CONFIG_CLK_QCOM_QCM2290=y
CONFIG_CLK_QCOM_QCS404=y
CONFIG_CLK_QCOM_QCS615=y
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 6/7] qcom_defconfig: Enable Milos clock driver
2026-03-11 14:20 ` [PATCH 6/7] qcom_defconfig: Enable Milos clock driver Luca Weiss
@ 2026-03-12 7:50 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:50 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:46PM +0100, Luca Weiss wrote:
> Enable the driver so that Milos devices can boot with qcom_defconfig.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> configs/qcom_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index fe5880de1fd..44c1cef725c 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -56,6 +56,7 @@ CONFIG_CLK=y
> CONFIG_CLK_STUB=y
> CONFIG_CLK_QCOM_APQ8016=y
> CONFIG_CLK_QCOM_APQ8096=y
> +CONFIG_CLK_QCOM_MILOS=y
> CONFIG_CLK_QCOM_QCM2290=y
> CONFIG_CLK_QCOM_QCS404=y
> CONFIG_CLK_QCOM_QCS615=y
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 7/7] board/qualcomm: add debug config fragment for Milos
2026-03-11 14:20 [PATCH 0/7] Qualcomm Milos SoC bringup Luca Weiss
` (5 preceding siblings ...)
2026-03-11 14:20 ` [PATCH 6/7] qcom_defconfig: Enable Milos clock driver Luca Weiss
@ 2026-03-11 14:20 ` Luca Weiss
2026-03-12 7:51 ` Sumit Garg
6 siblings, 1 reply; 15+ messages in thread
From: Luca Weiss @ 2026-03-11 14:20 UTC (permalink / raw)
To: Sumit Garg, u-boot, u-boot-qcom
Cc: Tom Rini, Casey Connolly, Neil Armstrong, Varadarajan Narayanan,
Aswin Murugan, Danila Tikhonov, David Wronek, Alexey Minnekhanov,
Lukasz Majewski, Aelin Reidel, Balaji Selvanathan, Jaehoon Chung,
Peng Fan, Rui Miguel Silva, Marek Vasut, Sam Day, Luca Weiss
Add a fragment similar to others to enable earlycon.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
board/qualcomm/debug-milos.config | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/board/qualcomm/debug-milos.config b/board/qualcomm/debug-milos.config
new file mode 100644
index 00000000000..a4cdd13f226
--- /dev/null
+++ b/board/qualcomm/debug-milos.config
@@ -0,0 +1,5 @@
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0xa94000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=14745600
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 7/7] board/qualcomm: add debug config fragment for Milos
2026-03-11 14:20 ` [PATCH 7/7] board/qualcomm: add debug config fragment for Milos Luca Weiss
@ 2026-03-12 7:51 ` Sumit Garg
0 siblings, 0 replies; 15+ messages in thread
From: Sumit Garg @ 2026-03-12 7:51 UTC (permalink / raw)
To: Luca Weiss
Cc: u-boot, u-boot-qcom, Tom Rini, Casey Connolly, Neil Armstrong,
Varadarajan Narayanan, Aswin Murugan, Danila Tikhonov,
David Wronek, Alexey Minnekhanov, Lukasz Majewski, Aelin Reidel,
Balaji Selvanathan, Jaehoon Chung, Peng Fan, Rui Miguel Silva,
Marek Vasut, Sam Day
On Wed, Mar 11, 2026 at 03:20:47PM +0100, Luca Weiss wrote:
> Add a fragment similar to others to enable earlycon.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> board/qualcomm/debug-milos.config | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
-Sumit
>
> diff --git a/board/qualcomm/debug-milos.config b/board/qualcomm/debug-milos.config
> new file mode 100644
> index 00000000000..a4cdd13f226
> --- /dev/null
> +++ b/board/qualcomm/debug-milos.config
> @@ -0,0 +1,5 @@
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_BASE=0xa94000
> +CONFIG_DEBUG_UART_MSM_GENI=y
> +CONFIG_DEBUG_UART_CLOCK=14745600
>
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread