[PATCH v5 0/8] riscv: Add support for P8700 platform on Boston board

Uros Stajic
2025-12-24T16:41:18Z

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Changes in v5:
- 01/08 - Drop p8700_platform_setup.S; move the early init logic to
harts_early_init()
- 02/08 - Add board_early_init_r() for Boston RISC-V.
- 02/08 - Defconfig/DT: set timebase-frequency to 25MHz, enable PCIe2 node,
and move bootargs to CONFIG_BOOTARGS
- 02/08 - Set CONFIG_PCI_BRIDGE_MEM_ALIGNMENT to avoid PCI BAR allocation
failures seen on Boston/P8700
- 02/08 - Drop GD_FLG_COHERENT_DMA; use a platform DMA-coherency check
instead
- 03/08 - Update eg20t-gpio driver to use the PCI API
- 05/08 - Refine the commit subject/body for the MIPS GIC syscon change
- 08/08 - Add p8700_dma_is_coherent() helper to determine whether DMA
is coherent
- Drop 'display' command patch
- Drop the 'startharts' command patch.

Changes in v4:
- 02/10 - Use riscv_aclint_timer and update CPU timer settings
- 03/10 - Fixed inconsistent empty line usage in gpio-eg20t driver
- 08/10 - Replaced inline assembly accessors with generic macros
- Dropped AMO instructions emulation patch
- Dropped P8700-specific timer patch

Changes in v3:
- 01/12 - Split original patch into CPU/Board parts
- 02/12 - New patch: extracted board-specific logic from original 01/12
- 01/12 - Relocated object rule for p8700 into p8700-specific Makefile
- 01/12 - Explained .word usage for mcache instruction and replaced it
with symbolic macro
- 01/12 - Replaced inline assembly lw instruction with readl()
- 01/12 - Removed p8700 code from start.S, moved to harts_early_init()
- 02/12 - Fixed operand spacing in assembly
- 02/12 - Replaced hardcoded address with properly macros
- 02/12 - Switched from riscv,isa to riscv,isa-extensions
- 02/12 - Sorted DT properties properly

Changes in v2:
- 03/11 - Remove redundant pcie_xilinx_probe() and update commit
message accordingly.
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Chao-ying Fu (8):
riscv: Add initial support for P8700 SoC
board: boston-riscv: Add initial support for P8700 Boston board
gpio: Add GPIO driver for Intel EG20T
pci: xilinx: Avoid writing memory base/limit for root bridge
riscv: Add syscon driver for MIPS GIC block
net: pch_gbe: Add PHY reset and MAC address fallback for RISC-V
libfdt: Allow non-64b aligned memreserve entries
riscv: p8700: Add Coherence Manager (CM) and IOCU support

arch/riscv/Kconfig | 23 ++
arch/riscv/cpu/p8700/Kconfig | 14 ++
arch/riscv/cpu/p8700/Makefile | 10 +
arch/riscv/cpu/p8700/cache.c | 99 ++++++++
arch/riscv/cpu/p8700/cm-iocu.c | 75 ++++++
arch/riscv/cpu/p8700/cm.c | 92 ++++++++
arch/riscv/cpu/p8700/cpu.c | 111 +++++++++
arch/riscv/cpu/p8700/dram.c | 37 +++
arch/riscv/cpu/p8700/p8700.c | 21 ++
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/boston-p8700.dts | 264 ++++++++++++++++++++++
arch/riscv/include/asm/arch-p8700/cm.h | 61 +++++
arch/riscv/include/asm/arch-p8700/p8700.h | 145 ++++++++++++
arch/riscv/include/asm/global_data.h | 4 +
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/mips_gic.c | 47 ++++
board/mips/boston-riscv/Kconfig | 47 ++++
board/mips/boston-riscv/MAINTAINERS | 11 +
board/mips/boston-riscv/Makefile | 9 +
board/mips/boston-riscv/boston-lcd.h | 20 ++
board/mips/boston-riscv/boston-regs.h | 38 ++++
board/mips/boston-riscv/boston-riscv.c | 30 +++
board/mips/boston-riscv/checkboard.c | 43 ++++
board/mips/boston-riscv/config.mk | 15 ++
board/mips/boston-riscv/iocu.c | 102 +++++++++
board/mips/boston-riscv/lowlevel_init.S | 18 ++
board/mips/boston-riscv/reset.c | 15 ++
configs/boston-p8700_defconfig | 98 ++++++++
drivers/clk/Kconfig | 2 +-
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 1 +
drivers/gpio/eg20t-gpio.c | 141 ++++++++++++
drivers/net/pch_gbe.c | 37 ++-
drivers/net/pch_gbe.h | 1 +
drivers/pci/pcie_xilinx.c | 9 +
include/configs/boston-riscv.h | 9 +
scripts/dtc/libfdt/fdt_ro.c | 11 +-
37 files changed, 1663 insertions(+), 6 deletions(-)
create mode 100644 arch/riscv/cpu/p8700/Kconfig
create mode 100644 arch/riscv/cpu/p8700/Makefile
create mode 100644 arch/riscv/cpu/p8700/cache.c
create mode 100644 arch/riscv/cpu/p8700/cm-iocu.c
create mode 100644 arch/riscv/cpu/p8700/cm.c
create mode 100644 arch/riscv/cpu/p8700/cpu.c
create mode 100644 arch/riscv/cpu/p8700/dram.c
create mode 100644 arch/riscv/cpu/p8700/p8700.c
create mode 100644 arch/riscv/dts/boston-p8700.dts
create mode 100644 arch/riscv/include/asm/arch-p8700/cm.h
create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h
create mode 100644 arch/riscv/lib/mips_gic.c
create mode 100644 board/mips/boston-riscv/Kconfig
create mode 100644 board/mips/boston-riscv/MAINTAINERS
create mode 100644 board/mips/boston-riscv/Makefile
create mode 100644 board/mips/boston-riscv/boston-lcd.h
create mode 100644 board/mips/boston-riscv/boston-regs.h
create mode 100644 board/mips/boston-riscv/boston-riscv.c
create mode 100644 board/mips/boston-riscv/checkboard.c
create mode 100644 board/mips/boston-riscv/config.mk
create mode 100644 board/mips/boston-riscv/iocu.c
create mode 100644 board/mips/boston-riscv/lowlevel_init.S
create mode 100644 board/mips/boston-riscv/reset.c
create mode 100644 configs/boston-p8700_defconfig
create mode 100644 drivers/gpio/eg20t-gpio.c
create mode 100644 include/configs/boston-riscv.h

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2.34.1