From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DEDEF532DD for ; Tue, 24 Mar 2026 05:42:53 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AF99B8063E; Tue, 24 Mar 2026 06:42:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="cRGB1LZm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AB8F08352B; Tue, 24 Mar 2026 06:42:50 +0100 (CET) Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5F40D805D7 for ; Tue, 24 Mar 2026 06:42:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@kernel.org Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 2C425600C4; Tue, 24 Mar 2026 05:42:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D5A26C2BC87; Tue, 24 Mar 2026 05:42:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774330966; bh=EQx2Omxj5fnsvDl7BenQDpMUqB2RxZgULO/J/nxHxl4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=cRGB1LZmQ39ac5qIVgtYwPolIM1jjhTyu9PhzY8q3rEQOHMpoTTKIdC1EXfjjMDih YODyBScFynzMCIL3RyiMQ7KXc78KgjFT9/UriaPpK7l6LQfVOou9HRCsJD9HkxTrZ/ EtLWJTNKAvWqCUm/znQ4avI0y6Ttc84PBTE7bOBmfQDkoTJc7Bz0k4g38eVHkW3oQD ZC1U0X/KPVBqbeMod82Q9zny4M8JrMkqDt0mlkbTvoji53i6m10uXog8hxLdDRvaH1 4m4p2+r5Go4ZVaOGrzCyzsDX+uMRBLs01E8NYxGBkeAaGIeeaZLrt/XbOgMD794nF/ 7joyexBdlIcrA== Date: Tue, 24 Mar 2026 11:12:37 +0530 From: Sumit Garg To: Luca Weiss Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io, Tom Rini , Casey Connolly , Neil Armstrong , Varadarajan Narayanan , Aswin Murugan , Danila Tikhonov , David Wronek , Alexey Minnekhanov , Lukasz Majewski , Aelin Reidel , Balaji Selvanathan , Jaehoon Chung , Peng Fan , Rui Miguel Silva , Marek Vasut , Sam Day , Ilias Apalodimas Subject: Re: [PATCH v2 2/7] clk/qcom: Add Milos clock driver Message-ID: References: <20260318-milos-bringup-v2-0-650b91dd75d8@fairphone.com> <20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Wed, Mar 18, 2026 at 01:46:28PM +0100, Luca Weiss wrote: > Add Clock driver for the GCC block found in the Milos SoC. > > The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref" > clock), so we need to pass that as well. > > Signed-off-by: Luca Weiss > --- > drivers/clk/qcom/Kconfig | 8 ++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clock-milos.c | 196 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 205 insertions(+) > Reviewed-by: Sumit Garg -Sumit > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 8504ed5d656..0a2ce55aaa2 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -47,6 +47,14 @@ config CLK_QCOM_IPQ9574 > on the Snapdragon IPQ9574 SoC. This driver supports the clocks > and resets exposed by the GCC hardware block. > > +config CLK_QCOM_MILOS > + bool "Qualcomm Milos GCC" > + select CLK_QCOM > + help > + Say Y here to enable support for the Global Clock Controller > + on the Snapdragon Milos SoC. This driver supports the clocks > + and resets exposed by the GCC hardware block. > + > config CLK_QCOM_QCM2290 > bool "Qualcomm QCM2290 GCC" > select CLK_QCOM > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 82a5b166196..b96d61b603e 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o > obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o > obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o > obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o > +obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o > obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o > obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o > obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o > diff --git a/drivers/clk/qcom/clock-milos.c b/drivers/clk/qcom/clock-milos.c > new file mode 100644 > index 00000000000..afe59108559 > --- /dev/null > +++ b/drivers/clk/qcom/clock-milos.c > @@ -0,0 +1,196 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Clock drivers for Qualcomm Milos > + * > + * (C) Copyright 2024 Linaro Ltd. > + * (C) Copyright 2026 Luca Weiss > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "clock-qcom.h" > + > +/* On-board TCXO, TOFIX get from DT */ > +#define TCXO_RATE 76800000 > + > +/* bi_tcxo_div4 divided after RPMh output */ > +#define TCXO_DIV4_RATE (TCXO_RATE / 4) > + > +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s3_clk_src[] = { > + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), > + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), > + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), > + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), > + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), > + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), > + F(51200000, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375), > + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), > + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), > + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), > + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), > + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), > + { } > +}; > + > +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { > + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), > + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), > + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), > + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), > + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), > + /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */ > + { } > +}; > + > +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { > + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), > + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), > + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), > + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), > + { } > +}; > + > +static ulong milos_set_rate(struct clk *clk, ulong rate) > +{ > + struct msm_clk_priv *priv = dev_get_priv(clk->dev); > + const struct freq_tbl *freq; > + > + switch (clk->id) { > + case GCC_QUPV3_WRAP0_S5_CLK: /* UART5 */ > + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s3_clk_src, rate); > + clk_rcg_set_rate_mnd(priv->base, 0x18500, > + freq->pre_div, freq->m, freq->n, freq->src, 16); > + return freq->freq; > + case GCC_SDCC2_APPS_CLK: > + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); > + clk_rcg_set_rate_mnd(priv->base, 0x14018, > + freq->pre_div, freq->m, freq->n, freq->src, 8); > + return freq->freq; > + case GCC_USB30_PRIM_MASTER_CLK: > + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); > + clk_rcg_set_rate_mnd(priv->base, 0x3902c, > + freq->pre_div, freq->m, freq->n, freq->src, 8); > + return freq->freq; > + case GCC_USB30_PRIM_MOCK_UTMI_CLK: > + clk_rcg_set_rate(priv->base, 0x39044, 0, 0); > + return TCXO_DIV4_RATE; > + default: > + return 0; > + } > +} > + > +static const struct gate_clk milos_clks[] = { > + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x39090, BIT(0)), > + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(27)), > + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x52008, BIT(20)), > + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x52008, BIT(21)), > + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14010, BIT(0)), > + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), > + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)), > + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), > + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), > + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), > +}; > + > +static int milos_enable(struct clk *clk) > +{ > + struct msm_clk_priv *priv = dev_get_priv(clk->dev); > + > + switch (clk->id) { > + case GCC_AGGRE_USB3_PRIM_AXI_CLK: > + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); > + break; > + } > + > + return qcom_gate_clk_en(priv, clk->id); > +} > + > +static const struct qcom_reset_map milos_gcc_resets[] = { > + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, > + [GCC_SDCC1_BCR] = { 0xa3000 }, > + [GCC_SDCC2_BCR] = { 0x14000 }, > + [GCC_UFS_PHY_BCR] = { 0x77000 }, > + [GCC_USB30_PRIM_BCR] = { 0x39000 }, > +}; > + > +static const struct qcom_power_map milos_gdscs[] = { > + [UFS_PHY_GDSC] = { 0x77004 }, > + [UFS_MEM_PHY_GDSC] = { 0x9e000 }, > + [USB30_PRIM_GDSC] = { 0x39004 }, > +}; > + > +static struct msm_clk_data milos_gcc_data = { > + .resets = milos_gcc_resets, > + .num_resets = ARRAY_SIZE(milos_gcc_resets), > + .clks = milos_clks, > + .num_clks = ARRAY_SIZE(milos_clks), > + .power_domains = milos_gdscs, > + .num_power_domains = ARRAY_SIZE(milos_gdscs), > + > + .enable = milos_enable, > + .set_rate = milos_set_rate, > +}; > + > +static const struct udevice_id gcc_milos_of_match[] = { > + { > + .compatible = "qcom,milos-gcc", > + .data = (ulong)&milos_gcc_data, > + }, > + { } > +}; > + > +U_BOOT_DRIVER(gcc_milos) = { > + .name = "gcc_milos", > + .id = UCLASS_NOP, > + .of_match = gcc_milos_of_match, > + .bind = qcom_cc_bind, > + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, > +}; > + > +static ulong milos_rpmh_clk_set_rate(struct clk *clk, ulong rate) > +{ > + return (clk->rate = rate); > +} > + > +static ulong milos_rpmh_clk_get_rate(struct clk *clk) > +{ > + switch (clk->id) { > + case RPMH_CXO_CLK: > + return TCXO_DIV4_RATE; > + default: > + return clk->rate; > + } > +} > + > +static int milos_rpmh_clk_nop(struct clk *clk) > +{ > + return 0; > +} > + > +static struct clk_ops milos_rpmh_clk_ops = { > + .set_rate = milos_rpmh_clk_set_rate, > + .get_rate = milos_rpmh_clk_get_rate, > + .enable = milos_rpmh_clk_nop, > + .disable = milos_rpmh_clk_nop, > +}; > + > +static const struct udevice_id milos_rpmh_clk_ids[] = { > + { .compatible = "qcom,milos-rpmh-clk" }, > + { } > +}; > + > +U_BOOT_DRIVER(milos_rpmh_clk) = { > + .name = "milos_rpmh_clk", > + .id = UCLASS_CLK, > + .of_match = milos_rpmh_clk_ids, > + .ops = &milos_rpmh_clk_ops, > + .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, > +}; > > -- > 2.53.0 >